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AN-8027
FAN480X PFC+PWM Combination Controller Application
FAN4800A / FAN4800C / FAN4801 / FAN4802 / FAN4802L
Introduction
This application note describes step-by-step design
considerations for a power supply using the FAN480X
controller. The FAN480X combines a PFC controller and
a PWM controller. The PFC controller employs average
current mode control for Continuous Conduction Mode
(CCM) boost converter in the front end. The PWM
controller can be used in either current mode or voltage
mode for the downstream converter. In voltage mode,
feed-forward from the PFC output bus can be used to
improve the line transient response of PWM stage. In
either mode, the PWM stage uses conventional trailing-
edge duty cycle modulation, while the PFC uses leading-
edge modulation. This proprietary leading/trailing-edge
modulation technique can significantly reduce the ripple
current of the PFC output capacitor.
The synchronization of the PWM with the PFC simplifies
the PWM compensation due to the controlled ripple on the
PFC output capacitor (the PWM input capacitor). In
addition to power factor correction, a number of protection
features have been built in to the FAN480X. These include
programmable soft-start, PFC over-voltage protection,
pulse-by-pulse current limiting, brownout protection, and
under-voltage lockout.
FAN4801/2/2L feature programmable two-level PFC
output to improve efficiency at light-load and low-line
conditions.
FAN480X is pin-to-pin compatible with FAN4800 and
ML4800, only requiring adjustment of some peripheral
components. The FAN480X series comparison is
summarized in the Appendix A.
F
1
AC
Input
L
BOOST
D
BOOST
C
BOOST
Q
1
V
BOUT
R
FB1
Drv
L
1
1
Q
2
D
R1
D
R1
D
F1
L
1
2
C
IF1
Vo1
Drv
R
CS1
R
RAMP
D1
D2
D
R2
Drv
C
O11
C
O12
L
22
L
2
D
F2
1
Vo2
Q
3
D
R2
C
O21
C
O22
C
IC2
R
LF1
R
T
R
RMS2
C
LF1
C
SS
R
B
R
LF2
R
CS2
R
IAC
R
IC
IEA
IAC
ISENSE
VRMS
SS
FBPWM
R
RMS1
C
RMS1
C
IC1
VEA
FBPFC
VREF
VD
D
OPFC
OPWM
GND
ILIMIT
R
D
Vo
1
R
BIAS
V
D
D
R
VC
C
VC2
C
VC1
C
F
R
F
R
OS1
Vo2
C
RMS2
R
RMS3
C
T
RT/CT
RAMP
R
OS2
R
OS3
FAN480X
C
RAMP
C
B
R
FB2
C
FB
C
LF2
C
DD
C
REF
Figure 1. Typical Application Circuit of FAN480X
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 8/26/09
www.fairchildsemi.com
AN-8027
Functional Description
Gain Modulator
The gain modulator is the key block for PFC stage because
it provides the reference to the current control error
amplifier for the input current shaping, as shown in Figure
2. The output current of gain modulator is a function of V
EA
,
I
AC
, and V
RMS
. The gain of the gain modulator is given in
the datasheet as a ratio between I
MO
and I
AC
with a given
V
RMS
when V
EA
is saturated to HIGH. The gain is inversely
proportional to V
RMS2
, as shown in Figure 3, to implement
line feed-forward. This automatically adjusts the reference
of current control error amplifier according to the line
voltage such that the input power of PFC converter is not
changed with line voltage.
V
IN
I
L
However, once PFC stops switching operation, the junction
capacitance of bridge diode is not discharged and V
IN
of
Figure 2 is clamped at the peak of the line voltage. Then,
the voltage of VRMS pin is given by:
V
RMS NS
=
V
LINE
2
R
RMS
3
R
RMS
1
+
R
RMS
2
+
R
RMS
3
(2)
Therefore, the voltage divider for VRMS should be
designed considering the brownout protection trip point
and minimum operation line voltage.
PFC runs
V
IN
PFC stops
IEA
R
ISENS
E
R
RMS1
R
IAC
C
RMS1
C
RMS2
I
AC
IA
C
VRMS
VEA
k
x
2
M
R
M
I
MO
=
G
⋅
I
AC
=
I
AC
⋅
K
⋅
(
V
EA
−
0.7)
V
RMS
2
(
V
EA MAX
−
0.7)
V
RMS
R
RMS2
R
RMS3
Gain
Modulator
Figure 4. V
RMS
According to the PFC Operation
Figure 2. Gain Modulator Block
The rectified sinusoidal signal is obtained by the current
flowing into the IAC pin. The resistor R
IAC
should be large
enough to prevent saturation of the gain modulator as:
2
V
LINE
.
BO
⋅
G
MAX
<
159
μ
A
(3)
R
IAC
where V
LINE.BO
is the line voltage that trips brownout
protection, G
MAX
is the maximum modulator gain when V
RMS
is 1.08V (which can be found in the datasheet), and 159µA is
the maximum output current of the gain modulator.
G
∝
1
V
RMS
2
Current and Voltage Control of Boost Stage
As shown in Figure 5, the FAN480X employs two control
loops for power factor correction: a current control loop
and a voltage control loop. The current control loop shapes
inductor current, as shown in Figure 6, based on the
reference signal obtained at the IAC pin as:
V
RMS
V
RMS-UVP
Figure 3. Modulation Gain Characteristics
I
L
⋅
R
CS
1
=
I
MO
⋅
R
M
=
I
AC
⋅
G
⋅
R
M
(4)
To sense the RMS value of the line voltage, an averaging
circuit with two poles is typically employed, as shown in
Figure 2. The voltage of VRMS pin in normal PFC
operation is given as:
V
RMS
=
V
LINE
2
R
RMS
3
2
⋅
R
RMS
1
+
R
RMS
2
+
R
RMS
3
π
(1)
where V
LINE
is RMS value of line voltage.
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 8/26/09
www.fairchildsemi.com
2
AN-8027
V
IN
I
L
V
O
It is typical to set the second boost output voltage as
340V~300V
.
R
CS1
R
F1
ISENSE
R
RMS1
R
IAC
C
RMS1
C
RMS2
I
AC
C
F1
IAC
VRMS
VEA
R
VC
R
VC2
FBPFC
R
VC1
2.5V
R
FB2
+
R
M
R
M
IEA
R
IC
I
MO
C
IC2
Drive logic
C
IC1
R
RMS2
VREF
R
RMS3
-
OPFC
R
FB1
Figure 7. Block of Two-Level PFC Output
Oscillator
The internal oscillator frequency of FAN480X is
determined by the timing resistor and capacitor on RT/CT
pin. The frequency of the internal oscillator is given by:
f
OSC
=
1
0.56
⋅
R
T
⋅
C
T
+
360
C
T
(6)
Figure 5. Gain Modulation Block
I
AC
I
MO
R
M
R
CS
1
I
L
Figure 6. Inductor Current Shaping
The voltage control loop regulates PFC output voltage
using internal error amplifier such that the FBPFC voltage
is same as internal reference of 2.5V.
Because the PWM stage of FAN480X generally uses a
forward converter, it is required to limit the maximum duty
cycle at 50%. To have a small tolerance of the maximum
duty cycle, a frequency divider with toggle flip-flops is
used, as illustrated in Figure 8. The operation frequency of
PFC and PWM stage is one quarter (1/4) of the oscillator
frequency. (For FAN4800C and FAN4802/2L, the
operation frequencies for PFC and PWM stages are one
quarter (1/4) and one half (1/2) of the oscillator frequency,
respectively).
The dead time for the PFC gate drive signal is determined
by the equation:
t
DEAD
=
360
C
T
(7)
Brownout Protection
FAN480X has a built-in internal brownout protection
comparator monitoring the voltage of the VRMS pin. Once
the VRMS pin voltage is lower than 1.05V (0.9V for
FAN4802L), the PFC stage is shutdown to protect the
system from over current. The FAN480X starts up the
boost stage once the V
RMS
voltage increases above 1.9V
(1.65V for FAN4802L).
The dead time should be smaller than 2% of switching
period to minimize line current distortion around line zero
crossing.
Two-Level PFC Output
To improve system efficiency at low AC line voltage and
light load condition, FAN480X provides two-level PFC
output voltage. As shown in Figure 7, FAN480X monitors
V
EA
and V
RMS
voltages to adjust the PFC output voltage.
When V
EA
and V
RMS
are lower than the thresholds, an
internal current source of 20
µ
A is enabled that flows
through R
FB2
, increasing the voltage of the FBPFC pin.
This causes the PFC output voltage to reduce when 20
µ
A
is enabled, calculated as:
VREF
RT/
CT
T-FF
T Q
T-FF
T
Q
OPFC, OPWM
OSC
OPWM (FAN4800C, FAN4802/2L)
Figure 8. Oscillator Configuration
V
OPFC
2
=
R
FB
1
+
R
FB
2
×
(2
.
5
-
20
μA
×
R
FB
2
)
R
FB
2
(5)
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3
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 8/26/09
AN-8027
RT/
CT
V
BOUT
REF
1.5V
RAMP
PWM
-
+
PFC dead time
R
RAMP
OPFC
C
RAMP
OPWM
FBPWM
OPWM (FAN4800C, FAN4802/2L)
Figure 9. FAN480X Timing Diagram
Figure 10. PWM Ramp Generation Circuit
PWM Stage
The PWM stage is capable of current-mode or voltage-
mode operation. In current-mode applications, the PWM
ramp (RAMP) is usually derived directly from a current
sensing resistor or current transformer in the primary of the
output stage and is thereby representative of the current
flowing in the converter’s output stage. I
LIMIT
, which
provides cycle-by-cycle current limiting, is typically
connected to RAMP in such applications.
For voltage-mode operation, RAMP can be connected to a
separate RC timing network to generate a voltage ramp
against which FBPWM voltage is compared. Under these
conditions, the use of voltage feed-forward from the PFC
bus can be used for better line transient response.
No voltage error amplifier is included in the PWM stage,
as this function is generally performed by a programmable
shunt regulator, such as KA431, in the secondary-side. To
facilitate the design of opto-coupler feedback circuitry, an
offset voltage is built into the inverting input of PWM
comparator that allows FBPWM to command a zero
percent duty cycle when its pin voltage is below 1.5V.
PWM Current Limit
The ILIMIT pin is a direct input to the cycle-by-cycle
current limiter for the PWM section. If the input voltage at
this pin exceeds 1V, the output of the PWM is disabled
until the start of the next PWM clock cycle.
V
IN
OK Comparator
The V
IN
OK comparator monitors the output of the PFC
stage and inhibits the PWM stage if this voltage is less than
2.4V (96% of its nominal value). Once this voltage goes
above 2.4V, the PWM stage begins to soft-start.
PWM Soft-Start (SS)
PWM startup is controlled by the soft-start capacitor. A
10µA current source supplies the charging current for the
soft-start capacitor. Startup of the PWM is prohibited until
the soft-start capacitor voltage reaches 1.5V.
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 8/26/09
www.fairchildsemi.com
4
AN-8027
Design Considerations
In this section, a design procedure is presented using the
schematic in Figure 11 as reference. A 300W PC power
supply application with universal input range is selected as
a design example. The design specifications are
summarized in 0. The two-switch forward converter is used
for DC/DC converter stage.
Design Specifications
Rated Voltage of Output 1
Rated Current of Output 1
Rated Voltage of Output 2
Rated Current of Output 2
Rated Voltage of Output 3
Rated Current of Output 3
Rated Voltage of Output 4
Rated Current of Output 4
Rated Output Power
Line Voltage Range
Line Frequency
Brownout Protection Line Voltage
Overall Stage Efficiency
V
OUT1
= 5V
I
OUT1
= 9A
V
out2
= 12V
I
OUT2
= 16.5A
V
OUT3
= -12V
I
OUT3
= 0.8A
V
OUT4
= 3.3V
I
OUT4
= 13.5A
P
O
= 300W
85~264V
AC
50Hz
72V
AC
η
= 0.82
PWM Stage Efficiency
Hold-up Time
Minimum PFC Output Voltage
Nominal PFC output voltage
PFC Output Voltage Ripple
PFC Inductor Ripple Current
AC Input Voltage Frequency
Switching Frequency
Total Harmonic Distortion
Magnetic Flux Density
Current Density
PWM Maximum Duty Cycle
5V Output Current Ripple
12V Output Current Ripple
F
1
AC
Input
L
BOOST
D
BOOST
C
BOOST
Q
1
V
BOUT
R
FB1
Drv
η
PWM
= 0.86
t
HLD
= 20ms
310V
V
O
_
PFC
= 387V
12V
PP
dI = 40%
f
line
= 50 ~ 60Hz
f
S
= 65KHz
α
= 4%
ΔB
= 0.27T
D
cma
= 400C-m/A
D
max
= 0.35
I
Lo1
= 44%
I
Lo2
= 10%
L
1
1
Q
2
D
R1
D
R1
D
F1
L
1
2
C
IF1
V
o1
Drv
R
CS1
R
RAMP
D1
D2
D
R2
Drv
C
O11
C
O12
L
22
L
2
D
F2
1
V
o2
Q
3
D
R2
C
O21
C
O22
C
IC2
R
LF1
R
T
R
RMS2
C
LF1
C
SS
R
B
R
LF2
R
CS2
V
o3
V
o4
R
IAC
R
IC
IEA
R
RMS1
C
RMS1
C
IC1
VEA
FBPFC
VREF
VD
D
OPFC
OPWM
GND
ILIMIT
R
D
V
o1
IAC
ISENSE
VRMS
SS
FBPWM
R
BIAS
V
D
D
R
VC
C
VC2
C
VC1
C
F
R
F
R
OS1
V
o2
C
RMS2
R
RMS3
C
T
RT/CT
RAMP
R
OS2
R
OS3
FAN480X
C
RAMP
C
B
R
FB2
C
FB
C
LF2
C
DD
C
REF
Figure 11. Reference Circuit for Design Example
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 8/26/09
www.fairchildsemi.com
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