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MC10H125
Quad MECL−to−TTL
Translator
Description
The MC10H125 is a quad translator for interfacing data and control
signals between the MECL section and saturated logic section of
digital systems. The 10H part is a functional/pinout duplication of the
standard MECL 10K™ family part, with 100% improvement in
propagation delay, and no increase in power−supply current.
Outputs of unused translators will go to low state when their inputs
are left open.
Features
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MARKING DIAGRAMS*
16
MC10H125L
AWLYYWW
CDIP−16
L SUFFIX
CASE 620A
1
•
Propagation Delay, 2.5 ns Typical
•
Voltage Compensated
•
Improved Noise Margin 150 mV
(Over Operating Voltage and Temperature Range)
•
MECL 10K Compatible
•
Pb−Free Packages are Available*
16
16
MC10H125P
AWLYYWWG
1
1
PDIP−16
P SUFFIX
CASE 648
10H125
ALYWG
SOEIAJ−16
CASE 966
1 20
20 1
PLLC−20
FN SUFFIX
CASE 775
A
WL, L
YY, Y
WW, W
G
10H125G
AWLYYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
February, 2006
−
Rev. 12
1
Publication Order Number:
MC10H125/D
MC10H125
2
3
6
7
10
11
14
15
4
5
12
13
V
BB
*
GND = Pin 16
V
CC
( +5.0 Vdc) = Pin 9
V
EE
(
−5.2
Vdc) = Pin 8
1
V
BB
A
in
A
in
A
out
B
out
B
in
B
in
V
EE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
D
in
D
in
D
out
C
out
C
in
C
in
V
CC
*V
BB
to be used to supply bias to the MC10H125
only and bypassed (when used) with 0.01
mF
to
0.1
mF
capacitor to ground (0 V). V
BB
can source <
1.0 mA.
Pin assignment is for Dual−in−Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables.
Figure 1. Logic Diagram
Figure 2. Pin Assignment
Table 1. DIP CONVERSION TABLES
16−Pin DIL to 20−Pin PLCC
16 PIN DIL
20 PIN PLCC
1
2
2
3
3
4
4
5
5
7
6
8
7
9
8
10
9
12
10
13
11
14
12
15
13
17
14
18
15
19
16
20
20−Pin DIL to 20−Pin PLCC
20 PIN DIL
20 PIN PLCC
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
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2
MC10H125
Table 2. MAXIMUM RATINGS
Symbol
V
EE
V
CC
V
I
T
A
T
stg
Power Supply (V
CC
= 5.0 V)
Power Supply (V
EE
=
−5.2
V)
Input Voltage (V
CC
= 5.0 V)
Operating Temperature Range
Storage Temperature Range
−
Plastic
−
Ceramic
Characteristic
Rating
−8.0
to 0
0 to +7.0
0 to V
EE
0 to +75
−55
to +150
−55
to +165
Unit
Vdc
Vdc
Vdc
°C
°C
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
Table 3. ELECTRICAL CHARACTERISTICS
(V
EE
=
−5.2
V +5%; V
CC
= 5.0 V + 5.0 %) (Note 2)
0°
Symbol
I
E
Characteristic
Negative Power
Supply Drain
Current
I
CCH
I
CCL
I
inH
I
CBO
V
OH
V
OL
V
IH
V
IL
I
OS
V
BB
V
CMR
Positive Power Supply
Drain Current
Input Current
Input Leakage Current
High Output Voltage
I
OH
=
−1.0
mA
Low Output Voltage
I
OL
= +20 mA
High Input Voltage (Note 1)
Low Input Voltage (Note 1)
Short Circuit Current
Reference Voltage
Common Mode
Range (Note 3)
−1.17
−1.95
60
−1.38
−
−0.84
−1.48
150
−1.27
−
−1.13
−1.95
60
−1.35
−0.81
−1.48
150
−1.25
−1.07
−1.95
50
−1.31
−0.735
−1.45
150
−1.19
Vdc
Vdc
mA
Vdc
V
−
0.5
−
0.5
−
0.5
Vdc
−
−
−
−
2.5
63
40
225
1.5
−
−
−
−
−
2.5
63
40
145
1.0
−
−
−
−
−
2.5
63
40
145
1.0
−
mA
mA
mA
mA
Vdc
Min
−
Max
44
Min
−
25°
Max
40
Min
−
75°
Max
44
Unit
mA
−2.85
to +0.3
Typical
V
PP
Input Sensitivity (Note 4)
150
mV
1. When V
BB
is used as the reference voltage.
2. Each MECL 10H™ series circuit has been designed to meet the specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is
maintained.
3. Differential input not to exceed 1.0 Vdc.
4. 150 mV
p−p
differential input required to obtain full logic swing on output.
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3
MC10H125
Table 4. AC CHARACTERISTICS
0°
Symbol
t
pd
t
r
t
f
Characteristic
Propagation Delay
Rise Time (Note 5)
Fall Time (Note 5)
Min
0.8
0.3
0.3
Max
3.3
1.2
1.2
Min
0.85
0.3
0.3
25°
Max
3.35
1.2
1.2
Min
0.9
0.3
0.3
75°
Max
3.4
1.2
1.2
Unit
ns
ns
ns
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Output Voltage = 1.0 V to 2.0 V. R
L
= 500
W
to GND and C
L
= 25 pF to GND. Refer to Figure 1.
APPLICATION
TTL RECEIVER
CHARACTERISTIC TEST
*C
L
includes
fixture
capacitance
C
L
*
R
L
AC TEST LOAD
GND
Figure 1. TTL Output Loading Used for Device Evaluation
APPLICATION INFORMATION
The MC10H125 incorporates differential inputs and
Schottky TTL “totem pole” outputs. Differential inputs
allow for use as an inverting/non−inverting translator or as
a differential line receiver. The V
BB
reference voltage is
available on Pin 1 for use in single−ended input biasing. The
outputs of the MC10H125 go to a low−logic level whenever
the inputs are left floating, and a high−logic output level is
achieved with a minimum input level of 150 mV
p−p
.
An advantage of this device is that MECL−level
information can be received, via balanced twisted pair lines,
in the TTL equipment. This isolates the MECL−logic from
the noisy TTL environment. Power supply requirements are
ground, +5.0 V and
−5.2
V.
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