E
T
T
T
T
T
T
PENTIUM® II XEON™ PROCESSOR
AT 400 AND 450 MHZ
T
Single Edge Contact (S.E.C.) cartridge
packaging technology; the S.E.C.
cartridge delivers high performance
processing and bus technology in mid
range to high end servers and
workstations
100 MHz system bus speeds data
transfer between the processor and
the system
Integrated high performance 16K
instruction and 16K data, nonblocking,
level-one cache
Available in 512K, 1 M, 2M unified,
nonblocking level-two cache
Enables systems which are scaleable
up to four processors and 64 GB of
physical memory
Binary compatible with applications
running on previous members of the
Intel microprocessor family
Optimized for 32-bit applications
running on advanced 32-bit operating
systems
Dynamic Execution micro architecture
Dual Independent Bus architecture:
Separate dedicated external 100 MHz
System Bus and dedicated internal
cache bus operating at full processor
core speed
Power Management capabilities
— System Management mode
— Multiple low-power states
SMBus interface to advanced
manageability features
T
T
T
T
The Intel
®
Pentium
®
II Xeon™ processor is designed for mid-range to high-end servers and workstations, and is
binary compatible with previous Intel Architecture processors. The Pentium II Xeon processor provides the best
performance available for applications running on advanced operating systems such as Windows* 95, Windows
NT, and UNIX*. The Pentium II Xeon processor is scalable to four processors in a multiprocessor system and
extends the power of the Pentium Pro processor with new features designed to make this processor the right
choice for powerful workstation, advanced server management, and mission-critical applications. Pentium II
Xeon processor-based workstations offer the memory architecture required by the most demanding workstation
applications and workloads. Specific features of the Pentium II Xeon processor address platform manageability
to meet the needs of a robust IT environment, maximize system up time and ensure optimal configuration and
operation of servers. The Pentium II Xeon processor enhances the ability of server platforms to monitor, protect,
and service the processor and its environment.
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement
of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products.
Information contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION 1995
June 1998
Order Number: 243770-003
PENTIUM® II XEON™ PROCESSOR AT 400 AND 450 MHZ
E
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.”
Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from
future changes to them.
The Pentium® II Xeon™ processor may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com
Copyright © Intel Corporation 1998.
* Third-party brands and names are the property of their respective owners.
2
E
PENTIUM® II XEON™ PROCESSOR AT 400 AND 450 MHZ
CONTENTS
PAGE
PAGE
3.3.1. 2.5 V TOLERANT BUFFER
OVERSHOOT/UNDERSHOOT
GUIDELINES........................................ 37
3.3.2. 2.5 V TOLERANT BUFFER RINGBACK
SPECIFICATION .................................. 38
3.3.3. 2.5 V TOLERANT BUFFER SETTLING
LIMIT GUIDELINE ................................ 38
4.0. PROCESSOR FEATURES............................. 38
4.1. Functional Redundancy Checking Mode ..... 38
4.2. Low Power States and Clock Control .......... 39
4.2.1. NORMAL STATE—STATE 1 ............... 39
4.2.2. AUTO HALT POWER DOWN
STATE—STATE 2................................ 39
4.2.3. STOP-GRANT STATE—STATE 3....... 40
4.2.4. HALT/GRANT SNOOP STATE—
STATE 4 ............................................... 40
4.2.5. SLEEP STATE—STATE 5 ................... 41
4.2.6. CLOCK CONTROL .............................. 41
4.3. System Management Bus (SMBus)
Interface ....................................................... 41
4.3.1. PROCESSOR INFORMATION ROM .. 42
4.3.2. SCRATCH EEPROM ........................... 45
4.3.3. PROCESSOR INFORMATION ROM
AND SCRATCH EEPROM
SUPPORTED SMBUS
TRANSACTIONS ................................. 45
4.3.4. THERMAL SENSOR ............................ 46
4.3.5. THERMAL SENSOR SUPPORTED
SMBUS TRANSACTIONS ................... 47
4.3.6. THERMAL SENSORS REGISTERS ... 49
4.3.6.1. Thermal Reference Registers........ 49
4.3.6.2. Thermal Limit Registers ................. 49
4.3.6.3. Status Register .............................. 49
4.3.6.4. Configuration Register ................... 49
4.3.6.5. Conversion Rate Register.............. 50
4.3.7. SMBUS DEVICE ADDRESSING ......... 50
5.0. THERMAL SPECIFICATIONS AND DESIGN
CONSIDERATIONS........................................ 52
5.1. Thermal Specifications................................. 52
5.1.1. POWER DISSIPATION ........................ 53
3
1.0. INTRODUCTION............................................... 8
1.1. Terminology .................................................... 8
1.1.1. S.E.C. Cartridge Terminology................. 8
1.2. References..................................................... 9
2.0. ELECTRICAL SPECIFICATIONS .................... 9
2.1. The Pentium® II Xeon™ Processor System
Bus and VREF ............................................... 9
2.2. Power and Ground Pins............................... 10
2.3. Decoupling Guidelines ................................. 10
2.3.1. PENTIUM® II XEON™ PROCESSOR
VCCCORE............................................ 11
2.3.2. LEVEL 2 CACHE DECOUPLING ........ 11
2.3.3. SYSTEM BUS AGTL+
DECOUPLING...................................... 11
2.4. System Bus Clock and Processor
Clocking ....................................................... 11
2.4.1. MIXING PROCESSORS OF
DIFFERENT FREQUENCIES AND
CACHE SIZES...................................... 14
2.5. Voltage Identification .................................... 14
2.6. System Bus Unused Pins and Test Pins ..... 16
2.7. System Bus Signal Groups.......................... 16
2.7.1. ASYNCHRONOUS VS.
SYNCHRONOUS FOR SYSTEM BUS
SIGNALS .............................................. 18
2.8. Test Access Port (TAP) Connection............ 18
2.9. Maximum Ratings ........................................ 18
2.10.
2.11.
2.12.
Processor DC Specifications .................. 19
AGTL+ System Bus Specifications ......... 23
System Bus AC Specifications ............... 24
3.0. SIGNAL QUALITY .......................................... 33
3.1. System Bus Clock Signal Quality
Specifications............................................... 34
3.2. AGTL+ Signal Quality Specifications........... 35
3.2.1. AGTL+ RINGBACK TOLERANCE
SPECIFICATIONS ............................... 35
3.2.2. AGTL+ OVERSHOOT/UNDERSHOOT
GUIDELINES........................................ 36
3.3. Non-AGTL+ Signal Quality Specifications ... 37
PENTIUM® II XEON™ PROCESSOR AT 400 AND 450 MHZ
5.1.2. PLATE FLATNESS
SPECIFICATION.................................. 54
5.2. Processor Thermal Analysis........................ 54
5.2.1. THERMAL SOLUTION
PERFORMANCE ................................. 54
5.2.2. THERMAL PLATE TO COOLING
SOLUTION INTERFACE
MANAGEMENT GUIDE ....................... 55
5.2.3. MEASUREMENTS FOR THERMAL
SPECIFICATIONS ............................... 57
5.2.3.1. Thermal Plate Temperature
Measurement ................................. 57
5.2.3.2. Cover Temperature Measurement
Guideline........................................ 58
6.0. MECHANICAL SPECIFICATIONS................. 58
6.1. Weight .......................................................... 63
6.2. Cartridge to Connector Mating Details......... 63
6.3. Pentium® II Xeon™ Processor Substrate
Edge Finger Signal Listing ........................... 65
7.0. BOXED PROCESSOR SPECIFICATIONS.... 74
7.1. Introduction................................................... 74
7.2. Mechanical Specifications ............................ 74
7.2.1. BOXED PROCESSOR HEATSINK
DIMENSIONS....................................... 77
7.2.2. BOXED PROCESSOR HEATSINK
WEIGHT ............................................... 78
7.2.3. BOXED PROCESSOR RETENTION
MECHANISM........................................ 78
7.3. Thermal Specifications ................................. 78
7.3.1. BOXED PROCESSOR COOLING
REQUIREMENTS ................................ 78
7.3.2. THERMAL EVALUATION .................... 78
8.0. INTEGRATION TOOLS .................................. 78
8.1. In-Target Probe (ITP) for Pentium® II
Xeon™ Processors...................................... 78
8.1.1. PRIMARY FUNCTION ......................... 79
8.1.2. DEBUG PORT CONNECTOR
DESCRIPTION..................................... 79
8.1.3. DEBUG PORT SIGNAL
DESCRIPTIONS .................................. 79
8.1.4. DEBUG PORT SIGNAL NOTES.......... 82
8.1.4.1. General Signal Quality Notes ........ 83
8.1.4.2. Signal Note: DBRESET# ............... 83
8.1.4.3. Signal Note: TDO and TDI............. 83
4
8.1.4.4. Signal Note: TCK ........................... 83
8.1.5. USING BOUNDARY SCAN TO
COMMUNICATE TO THE
PROCESSOR....................................... 85
8.2. Integration Tool (Logic Analyzer)
Considerations ............................................. 85
8.2.1. INTEGRATION TOOL MECHANICAL
KEEPOUTS .......................................... 85
9.0. APPENDIX ...................................................... 86
9.1. Alphabetical Signals Reference.................... 86
9.1.1. A[35:03]# (I/O) ...................................... 86
9.1.2. A20M# (I) .............................................. 86
9.1.3. ADS# (I/O) ............................................ 86
9.1.4. AERR# (I/O).......................................... 86
9.1.5. AP[1:0]# (I/O)........................................ 86
9.1.6. BCLK (I) ................................................ 87
9.1.7. BERR# (I/O).......................................... 87
9.1.8. BINIT# (I/O) .......................................... 87
9.1.9. BNR# (I/O) ............................................ 87
9.1.10.
9.1.11.
9.1.12.
9.1.13.
9.1.14.
9.1.15.
9.1.16.
9.1.17.
9.1.18.
9.1.19.
9.1.20.
9.1.21.
9.1.22.
9.1.23.
9.1.24.
9.1.25.
9.1.26.
9.1.27.
9.1.28.
9.1.29.
9.1.30.
9.1.31.
9.1.32.
BP[3:2]# (I/O) ................................... 87
BPM[1:0]# (I/O) ................................ 87
BPRI# (I)........................................... 87
BR0# (I/O), BR[3:1]# (I).................... 87
D[63:00]# (I/O).................................. 89
DBSY# (I/O) ..................................... 89
DEFER# (I)....................................... 89
DEP[7:0]# (I/O)................................. 89
DRDY# (I/O)..................................... 89
EMI ................................................... 89
FERR# (O) ....................................... 89
FLUSH# (I) ....................................... 89
FRCERR (I/O).................................. 89
HIT# (I/O), HITM# (I/O) .................... 90
IERR# (O) ........................................ 90
IGNNE# (I) ....................................... 90
INIT# (I) ............................................ 90
INTR - SEE LINT[0].......................... 90
LINT[1:0] (I) ...................................... 90
LOCK# (I/O) ..................................... 91
NMI - SEE LINT[1] ........................... 91
PICCLK (I)........................................ 91
PICD[1:0] (I/O) ................................. 91
E
E
9.1.33.
9.1.34.
9.1.34.
9.1.35.
9.1.37.
9.1.38.
9.1.39.
9.1.40.
9.1.41.
9.1.42.
9.1.43.
9.1.44.
9.1.45.
9.1.46.
9.1.47.
9.1.48.
9.1.49.
9.1.50.
9.1.51.
9.1.52.
9.1.53.
9.1.54.
9.1.55.
9.1.56.
9.1.57.
9.1.58.
9.1.59.
9.1.60.
PENTIUM® II XEON™ PROCESSOR AT 400 AND 450 MHZ
Figure 9. System Bus Reset and Configuration
Timings ............................................... 32
Figure 10. Power-On Reset and Configuration
Timings ............................................... 32
Figure 11. Test Timings (Boundary Scan) .......... 33
Figure 12. Test Reset Timings ............................ 33
Figure 13. BCLK, TCK, PICCLK Generic Clock
Waveform at the Processor Core
Pins ..................................................... 34
Figure 14. Low to High AGTL+ Receiver
Ringback Tolerance............................ 36
Figure 15. Non-AGTL+ Overshoot/Undershoot,
Settling Limit, and Ringback ............... 37
Figure 16. Stop Clock State Machine.................. 40
Figure 17. Logical Schematic of SMBus
Circuitry............................................... 42
Figure 18. Thermal Plate View ............................ 52
Figure 19. Plate Flatness Reference................... 54
Figure 20. Interface Agent Dispensing Areas
and Thermal Plate Temperature
Measurement Points ........................... 56
Figure 21. Technique for Measuring TPLATE
with 0° Angle Attachment.................... 57
Figure 22. Technique for Measuring TPLATE
with 90° Angle Attachment.................. 57
Figure 23. Guideline Locations for Cover
Temperature (TCOVER)
Thermocouple Placement................... 58
Figure 24. Isometric View of Pentium® II Xeon™
Processor S.E.C. Cartridge ................ 59
Figure 25. S.E.C. Cartridge Cooling Solution
Attach Details...................................... 60
Figure 26. S.E.C. Cartridge Retention Enabling
Details ................................................. 61
Figure 27. SEC Cartridge Retention Enabling
Details ................................................. 62
Figure 28. Side View of Connector Mating
Details ................................................. 63
Figure 29. Top View of Cartridge Insertion
Pressure Points .................................. 64
Figure 30. Front View of Connector Mating
Details ................................................. 64
Figure 31. Boxed Pentium® II Xeon™
Processor............................................ 75
Figure 32. Side View Space Requirements for
the Boxed Processor .......................... 76
Figure 33. Front View Space Requirements for
the Boxed Processor .......................... 77
5
PRDY# (O)....................................... 91
PWREN[1:0] (I) ................................ 91
PWRGOOD (I) ................................. 91
REQ[4:0]# (I/O) ................................ 92
RESET# (I)....................................... 92
RP# (I/O) .......................................... 92
RS[2:0]# (I)....................................... 92
RSP# (I) ........................................... 92
SA[2:0] (I) ......................................... 93
PREQ# (I)......................................... 91
SMBALERT# (O) ............................. 93
SMBCLK (I) ...................................... 93
SMBDAT (I/O).................................. 93
SELFSB0 (I/O) ................................. 93
SLP# (I) ............................................ 93
SMI# (I)............................................. 93
STPCLK# (I)..................................... 94
TCK (I).............................................. 94
TDI (I) ............................................... 94
TDO (O) ........................................... 94
TEST_25_A62 (I) ............................. 94
TEST_VCC_CORE_XXX (I)............ 94
THERMTRIP# (O)............................ 94
TMS (I) ............................................. 94
TRDY# (I) ......................................... 94
TRST# (I) ......................................... 94
VID_L2[4:0], VID_CORE[4:0](O) ..... 94
WP (I) ............................................... 95
9.2. Signal Summaries ........................................ 95
FIGURES
Figure 1. Timing Diagram of Clock Ratio
Signals ................................................ 13
Figure 2. Logical Schematic for Clock Ratio Pin
Sharing................................................ 13
Figure 3. I-V Curve for nMOS Device ................. 22
Figure 4. BCLK, PICCLK, TCK Generic Clock
Waveform ........................................... 29
Figure 5. SMBCLK Clock Waveform .................. 30
Figure 6. Valid Delay Timings ............................. 30
Figure 7. Setup and Hold Timings....................... 31
Figure 8. FRC Mode BCLK to PICCLK Timing ... 31
MicroPython Open Source section
京公网安备 11010802033920号
EEWORLD
