The SY10/100E193 are error detection and correction
(EDAC) circuits designed for use in new, high- performance
ECL systems. The E193 generates hamming parity codes
on an 8-bit word as shown in the block diagram. The P
5
output gives the parity of the whole word. PGEN provides
word parity after Odd/Even parity control and gating with
the BPAR input. PGEN also feeds into a 1-bit shiftable
register for use as part of a scan ring.
The combinatorial part of the device generates the same
code pattern as the Motorola MC10193.
Used in conjunction with 12-bit parity generators, such
as the E160, a SECDED (single error correction, double
error detection) error system can be designed for a multiple
of an 8-bit word.
PIN CONFIGURATION
S-IN
SHIFT
EN
HOLD
V
CCO
PGEN
PIN NAMES
Pin
B
0
–B
7
BPAR
Function
Check Bit Inputs
Check Bit Parity Input
Even/Odd Parity Select
Parity Enable
Syndrome Hold Input
Syndrome Bit Input
Syndrome Bit Shift
Clock Input
Parity Output
Parity Generate Output
Parity Error Output
V
CC
to Output
CLK
25 24 23 22 21 20 19
EV/OD
18
17
EV/OD
BPAR
B
0
V
EE
B
1
B
2
B
3
26
27
28
1
2
3
4
5
6
7
8
9
10 11
PARERR
PARERR
V
CC
P
5
V
CCO
P
4
P
3
EN
HOLD
S-IN
SHIFT
CLK
P
1
–P
5
PGEN
PARERR/PARERR
V
CCO
TOP VIEW
PLCC
J28-1
16
15
14
13
12
V
CCO
P
1
P
2
B
4
B
5
B
6
B
7
Rev.: C
Amendment: /1
1
Issue Date: February, 1998
Micrel
SY10E193
SY100E193
BLOCK DIAGRAM
B INPUTS
0 3 6 5 7 4 2 1
B2, B3, B6, B7
P
2
B1, B3, B5, B7
P
1
B4, B5, B6, B7
P
3
B1, B2, B4, B7
P
4
BYTE (B0 – B7)
P
5
BPAR
EV/OD
PGEN
0
EN
HOLD
S-IN
SHIFT
CLK
1
0
1
D
PARERR
PARERR
2
Micrel
SY10E193
SY100E193
DC ELECTRICAL CHARACTERISTICS
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
T
A
= 0
°
C
Symbol
I
IH
I
EE
Parameter
Input HIGH Current
Power Supply Current
10E
100E
—
—
112
112
134
134
—
—
112
112
134
134
—
—
112
129
134
155
—
—
150
T
A
= +25
°
C
—
—
150
T
A
= +85
°
C
Max.
150
Unit
µA
mA
Condition
—
—
—
—
Min. Typ. Max. Min. Typ.
Max. Min. Typ.
AC ELECTRICAL CHARACTERISTICS
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
T
A
= 0
°
C
Symbol
t
PLH
t
PHL
Parameter
Propagation Delay to Output
B to P
1
, P
2
, P
3
, P
4
B to P5
EV/OD, BPAR to PGEN
B to PGEN
CLK to PARERR
Set-up Time
SHIFT
S-IN
HOLD
EN
EV/OD
BPAR
B
Hold Time
SHIFT
S-IN
HOLD
EN
EV/OD
BPAR
B
Rise/Fall Time
20% to 80%
T
A
= +25
°
C
T
A
= +85
°
C
Max.
1000
1150
850
1450
850
ps
400 150
300
50
750 350
500 250
1300 850
1300 850
1700 1100
200
300
100
100
–200
–200
–300
300
–150
–50
–350
–250
–850
–850
–1100
700
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1100
400 150
300
50
750 350
500 250
1300 850
1300 850
1700 1100
200
300
100
100
–200
–200
–300
300
–150
–50
–350
–250
–850
–850
–1100
700
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1100
400 150
300
50
750 350
500 250
1300 850
1300 850
1700 1100
200
300
100
100
–200
–200
–300
300
–150
–50
–350
–250
–850
–850
–1100
700
—
—
—
—
—
—
—
ps
—
—
—
—
—
—
—
1100
ps
—
—
—
Unit
ps
350
400
350
600
300
700 1000
775 1150
650 850
1000 1450
550 850
350
400
350
600
300
700
775
650
1000
550
1000
1150
850
1450
850
350
400
350
600
300
700
775
650
1000
550
Condition
—
Min. Typ. Max. Min. Typ.
Max. Min. Typ.
t
S
t
H
t
r
t
f
PRODUCT ORDERING CODE
Ordering
Code
SY10E193JC
SY10E193JCTR
SY100E193JC
SY100E193JCTR
Package
Type
J28-1
J28-1
J28-1
J28-1
Operating
Range
Commercial
Commercial
Commercial
Commercial
3
Micrel
SY10E193
SY100E193
28 LEAD PLCC (J28-1)
Rev. 03
MICREL-SYNERGY
TEL
3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
FAX
+ 1 (408) 980-9191
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
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