IDT71V65602S150BGI datasheet, PDF

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IDT71V65602S150BGI: DescriptionZBT SRAM, 256KX36, 3.8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119; Categorystorage storage; File Size499KB，26 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT71V65602S150BGI Overview

ZBT SRAM, 256KX36, 3.8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119

IDT71V65602S150BGI Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	14 X 22 MM, PLASTIC, BGA-119
Contacts	119
Reach Compliance Code	not_compliant
ECCN code	3A991.B.2.A
Maximum access time	3.8 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	150 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	9437184 bit
Memory IC Type	ZBT SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	256KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA119,7X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
power supply	2.5,3.3 V
Certification status	Not Qualified
Maximum seat height	2.36 mm
Maximum standby current	0.06 A
Minimum standby current	3.14 V
Maximum slew rate	0.345 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn63Pb37)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	20
width	14 mm

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256K x 36, 512K x 18

3.3V Synchronous ZBT™ SRAMs

2.5V I/O, Burst Counter

Pipelined Outputs

IDT71V65602

IDT71V65802

Features

256K x 36, 512K x 18 memory configurations

Supports high performance system speed - 150MHz

(3.8ns Clock-to-Data Access)

ZBT

Feature - No dead cycles between write and read cycles

Internally synchronized output buffer enable eliminates the

need to control

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW

) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%)

2.5V I/O Supply (V

DDQ

)

Power down controlled by ZZ input

Packaged in a JEDEC standard 100-pin plastic thin quad and

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA)

Description

The IDT71V65602/5802 are 3.3V high-speed 9,437,184-bit

(9 Megabit) synchronous SRAMs. They are designed to eliminate dead

bus cycles when turning the bus around between reads and writes, or

writes and reads. Thus, they have been given the name ZBT

, or Zero

Bus Turnaround.

Address and control signals are applied to the SRAM during one clock

cycle, and two cycles later the associated data cycle occurs, be it read or write.

The IDT71V65602/5802 contain data I/O, address and control signal

registers. Output enable is the only asynchronous signal and can be used to

disable the outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V65602/5802

to be suspended as long as necessary. All synchronous inputs are ignored

when (CEN) is high and the internal device registers will hold their previous

values.

There are three chip enable pins (CE

, CE

) that allow the

user to deselect the device when desired. If any one of these three are not

asserted when ADV/LD is low, no new memory operation can be initiated.

However, any pending data transfers (reads or writes) will be completed. The

data bus will tri-state two cycles after chip is deselected or a write is initiated.

The IDT71V65602/5802 have an on-chip burst counter. In the burst

mode, the IDT71V65602/5802 can provide four cycles of data for a single

address presented to the SRAM. The order of the burst sequence is defined

by the

LBO

input pin. The

LBO

pin selects between linear and interleaved burst

sequence. The ADV/LD signal is used to load a new external address (ADV/

= LOW) or increment the internal burst counter (ADV/LD = HIGH).

The IDT71V65602/5802 SRAM utilize IDT's latest high-performance

CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm 100-

pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA)

and a 165 fine pitch ball grid array (fBGA).

Pin Description Summary

-A

1 8

, CE

R/W

CEN

CLK

A DV /LD

LBO

I/O

-I/O

3 1

, I/O

P 1

-I/O

P 4

D D

, V

D DQ

A d d re ss Inp uts

Chip E nab le s

Outp ut E nab le

Re ad /Write S ig nal

Clo c k E nab le

Ind ivid ual B yte W rite S e le cts

Clo ck

A d v ance b urst ad d re ss / Lo ad ne w ad d re ss

Line ar / Inte rle ave d B urst Ord e r

S le e p M o d e

Data Inp ut / Outp ut

Co re P o we r, I/O P o we r

Gro und

Inp ut

I/O

S up p ly

S ynchro no us

A s ynchro no us

S ynchro no us

N/A

S ynchro no us

S tatic

A s ynchro no us

S ynchro no us

S tatic

5303 tbl 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.

DECEMBER 2002

DSC-5303/04

IDT71V65602S150BGI Related Products

	IDT71V65602S150BGI	IDT71V65602S100BGI	IDT71V65802S133PFI	IDT71V65802S150BGI	IDT71V65602S150BQI
Description	ZBT SRAM, 256KX36, 3.8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119	ZBT SRAM, 256KX36, 5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119	ZBT SRAM, 512KX18, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	ZBT SRAM, 512KX18, 3.8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119	ZBT SRAM, 256KX36, 3.8ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	BGA	BGA	QFP	BGA	BGA
package instruction	14 X 22 MM, PLASTIC, BGA-119	14 X 22 MM, PLASTIC, BGA-119	14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	14 X 22 MM, PLASTIC, BGA-119	13 X 15 MM, FPBGA-165
Contacts	119	119	100	119	165
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	3.8 ns	5 ns	4.2 ns	3.8 ns	3.8 ns
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	150 MHz	100 MHz	133 MHz	150 MHz	150 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-PBGA-B119	R-PBGA-B119	R-PQFP-G100	R-PBGA-B119	R-PBGA-B165
JESD-609 code	e0	e0	e0	e0	e0
length	22 mm	22 mm	20 mm	22 mm	15 mm
memory density	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit
Memory IC Type	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM
memory width	36	36	18	18	36
Humidity sensitivity level	3	3	3	3	3
Number of functions	1	1	1	1	1
Number of terminals	119	119	100	119	165
word count	262144 words	262144 words	524288 words	524288 words	262144 words
character code	256000	256000	512000	512000	256000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
organize	256KX36	256KX36	512KX18	512KX18	256KX36
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	LQFP	BGA	TBGA
Encapsulate equivalent code	BGA119,7X17,50	BGA119,7X17,50	QFP100,.63X.87	BGA119,7X17,50	BGA165,11X15,40
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY	GRID ARRAY	FLATPACK, LOW PROFILE	GRID ARRAY	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	225	225	240	225	225
power supply	2.5,3.3 V	2.5,3.3 V	2.5,3.3 V	2.5,3.3 V	2.5,3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.36 mm	2.36 mm	1.6 mm	2.36 mm	1.2 mm
Maximum standby current	0.06 A	0.06 A	0.06 A	0.06 A	0.06 A
Maximum slew rate	0.345 mA	0.27 mA	0.32 mA	0.345 mA	0.345 mA
Maximum supply voltage (Vsup)	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)
Terminal form	BALL	BALL	GULL WING	BALL	BALL
Terminal pitch	1.27 mm	1.27 mm	0.65 mm	1.27 mm	1 mm
Terminal location	BOTTOM	BOTTOM	QUAD	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	20	20	20	20	20
width	14 mm	14 mm	14 mm	14 mm	13 mm
Minimum standby current	3.14 V	3.14 V	-	-	3.14 V
Base Number Matches	-	1	1	1	-

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