64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating)
Operated at Commercial and Industrial Temperature Ranges.
PRELIMINARY
PRELIMINARY
for AT&T
CMOS SRAM
Revision History
Rev. No.
Rev. 0.0
Rev. 0.1
Rev. 0.2
Rev. 1.0
History
Initial document.
Speed bin modify
Current modify
1. Final datasheet release
2. Delete 12ns speed bin.
3. Change Icc for Industrial mode.
Item
Previous
8ns
100mA
I
CC(Industrial)
10ns
85mA
1. Delete UB,LB releated timing diagram.
1. Add the Lead Free Package type.
Draft Data
May. 11. 2001
June. 18. 2001
September. 9. 2001
December. 18. 2001
Current
90mA
75mA
June. 19. 2002
July. 26, 2004
Final
Final
Remark
Preliminary
Preliminary
Preliminary
Final
Rev. 2.0
Rev. 3.0
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev. 3.0
July 2004
K6R1004V1D
1Mb Async. Fast SRAM Ordering Information
Org.
256K x4
Part Number
K6R1004C1D-J(K)C(I) 10
K6R1004V1D-J(K)C(I) 08/10
K6R1008C1D-J(K,T,U)C(I) 10
128K x8
K6R1008V1D-J(K,T,U)C(I) 08/10
K6R1016C1D-J(K,T,U,E)C(I) 10
64K x16
K6R1016V1D-J(K,T,U,E)C(I) 08/10
3.3
5
3.3
8/10
10
8/10
VDD(V)
5
3.3
5
Speed ( ns )
10
8/10
10
PKG
J : 32-SOJ
K: 32-SOJ(LF)
J : 32-SOJ
K : 32-SOJ(LF)
T : 32-TSOP2
U : 32-TSOP2(LF)
J : 44-SOJ
K : 44-SOJ(LF)
T : 44-TSOP2
U : 44-TSOP2(LF)
E : 48-TBGA
PRELIMINARY
PRELIMINARY
for AT&T
CMOS SRAM
Temp. & Power
C : Commercial Temperature
,Normal Power Range
I : Industrial Temperature
,Normal Power Range
-2-
Rev. 3.0
July 2004
K6R1004V1D
FEATURES
• Fast Access Time 8,10ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 20mA(Max.)
(CMOS) : 5mA(Max.)
Operating
//K6R1004V1D-08:
80mA(Max.)
K6R1004V1D-10: 65mA(Max.)
• Single 3.3±0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration :
K6R1004V1D-J : 32-SOJ-400
K6R1004V1D-K : 32-SOJ-400 (Lead-Free)
• Operating in Commercial and Industrial Temperature range.
PRELIMINARY
PRELIMINARY
for AT&T
CMOS SRAM
256K x 4 Bit (with OE) High-Speed CMOS Static RAM(3.3V Operating)
GENERAL DESCRIPTION
The K6R1004V1D is a 1,048,576-bit high-speed Static Random
Access Memory organized as 262,144 words by 4 bits.
The K6R1004V1D uses 4 common input and output lines and
has an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using
SAMSUNG′s advanced CMOS process and designed for
high-speed circuit technology. It is particularly well suited for
use in high-density high-speed system applications. The
K6R1004V1D is packaged in a 400 mil 32-pin plastic SOJ.
PIN CONFIGURATION
(Top View)
N.C
1
2
3
4
5
6
7
8
9
32 A
17
31 A
16
30 A
15
29 A
14
28 A
13
27
OE
26 I/O
4
FUNCTIONAL BLOCK DIAGRAM
A
0
A
1
A
2
Clk Gen.
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
Pre-Charge Circuit
A
3
CS
I/O
1
Vcc
Row Select
Vss
SOJ
25 Vss
24 Vcc
23 I/O
3
22 A
12
21
A
11
20 A
10
19
18
A
9
A
8
Memory Array
512 Rows
512x4 Columns
I/O
2
10
WE
A
4
A
5
A
6
11
12
13
14
15
I/O
1
~ I/O
4
Data
Cont.
CLK
Gen.
I/O Circuit &
Column Select
A
7
N.C 16
17 N.C
PIN FUNCTION
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
Pin Name
A
0
- A
17
WE
CS
OE
I/O
1
~ I/O
4
V
CC
V
SS
N.C
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power(+3.3V)
Ground
No Connection
CS
WE
OE
-3-
Rev. 3.0
July 2004
K6R1004V1D
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Commercial
Industrial
Symbol
V
IN
, V
OUT
V
CC
P
d
T
STG
T
A
T
A
Rating
-0.5 to 4.6
-0.5 to 4.6
1
-65 to 150
0 to 70
-40 to 85
PRELIMINARY
PRELIMINARY
for AT&T
CMOS SRAM
Unit
V
V
W
°C
°C
°C
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
=0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
3.0
0
2.0
-0.3*
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+0.3**
0.8
Unit
V
V
V
V
* V
IL
(Min) = -2.0V a.c (Pulse Width
≤
8ns) for I
≤
20mA.
** V
IH
(Max) = V
CC
+ 2.0V a.c (Pulse Width
≤
8ns) for I
≤
20mA.
DC AND OPERATING CHARACTERISTICS*
(T
A
=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
I
LI
I
LO
I
CC
V
IN
=V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
=V
SS
to V
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
=V
IH
or V
IL,
I
OUT
=0mA
Com.
Ind.
Standby Current
I
SB
I
SB1
Output Low Voltage Level
Output High Voltage Level
V
OL
V
OH
Min. Cycle, CS=V
IH
f=0MHz, CS≥V
CC
-0.2V,
V
IN
≥V
CC
-0.2V or V
IN
≤0.2V
I
OL
=8mA
I
OH
=-4mA
8ns
10ns
8ns
10ns
Test Conditions
Min
-2
-2
-
-
-
-
-
-
-
2.4
Max
2
2
80
65
90
75
20
5
0.4
-
V
V
mA
Unit
µA
µA
mA
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*
(T
A
=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
* Capacitance is sampled and not 100% tested.
Symbol
C
I/O
C
IN
Test Conditions
V
I/O
=0V
V
IN
=0V
TYP
-
-
Max
8
6
Unit
pF
pF
-4-
Rev. 3.0
July 2004
K6R1004V1D
AC CHARACTERISTICS
(T
A
=0 to 70°C, V
CC
=3.3±0.3V, unless otherwise noted.)
TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
PRELIMINARY
PRELIMINARY
for AT&T
CMOS SRAM
Value
0V to 3V
3ns
1.5V
See below
Output Loads(A)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
R
L
= 50Ω
+3.3V
D
OUT
V
L
= 1.5V
Z
O
= 50Ω
30pF*
D
OUT
319Ω
353
Ω
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Selection to Power DownTime
Symbol
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
PU
t
PD
K6R1004V1D-08
K6R1004V1D-10
Min
8
-
-
-
3
0
0
0
3
0
-
Max
-
8
8
4
-
-
4
4
-
-
8
Min
10
-
-
-
3
0
0
0
3
0
-
Max
-
10
10
5
-
-
5
5
-
-
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* The above parameters are also guaranteed at industrial temperature range.
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