N-Channel JFET Switch
CORPORATION
2N4391 – 2N4393 / PN4391 – PN4393 / SST4391 – SST4393
FEATURES
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25
o
C unless otherwise noted)
Gate-Source or Gate-Drain Voltage . . . . . . . . . . . . . . . . -40V
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Storage Temperature Range . . . . . . . . . . . . . -65
o
C to +200
o
C
Operating Temperature Range . . . . . . . . . . . -55
o
C to +200
o
C
Lead Temperature (Soldering, 10sec) . . . . . . . . . . . . . +300
o
C
TO-18
TO-92
SOT-23
Power Dissipation
1.8W
360mW
350mW
Derate above 25
o
C 10mW/
o
C 3.3mW/
o
C 2.8mW/
o
C
Plastic
Storage. . . . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +150
o
C
Operating . . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +135
o
C
NOTE:
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
G,C
D
S
S D
G
D S
G
•
r
ds(on)
<300 Ohms (2N4391)
•
I
D(OFF)
<100pA
•
Switches
±10VAC
With
±15V
Supplies (4392, 4393)
PIN CONFIGURATION
TO - 92
TO-18
TO-92
ORDERING INFORMATION
Part
Package
Hermetic TO-18
Plastic TO-92
Plastic SOT-23
Sorted Chips in Carriers
Temperature Range
-55
o
C to +200
o
C
-55
o
C to +135
o
C
-55
o
C to +135
o
C
-55
o
C to +200
o
C
2N4391/93
PN4391/93
SST4391/93
X2N4391/93
5001
G
SOT-23
D
S
PRODUCT MARKING (SOT-23)
SST4391
SST4392
SST4393
N01
N02
N03
CORPORATION
2N4391 – 2N4393 / PN4391 – PN4393
SST4391 – SST4393
ELECTRICAL CHARACTERISTICS
(T
A
= 25
o
C unless otherwise specified)
SYMBOL
PARAMETER
4391
-100
I
GSS
BV
GSS
Gate Reverse Current
-200
Gate-Source Breakdown Voltage
-40
100
I
D(off
)
Drain Cutoff Current
200
V
GS(f)
V
GS(off)
I
DSS
V
DS(on)
r
DS(on)
r
ds(on)
C
iss
Gate-Source Forward Voltage
Gate-Source Cutoff Voltage
Saturation Drain Current (Note 1)
Drain-Source ON Voltage
Static Drain-Source ON
Resistance
Drain-Source ON Resistance
Common-Source Input
Capacitance (Note 2)
Common-Source Reverse
Transfer Capacitance (Note 2)
3.5
t
d
t
r
t
off
t
f
Turn-ON Delay Time (Note 2)
Rise Time (Note 2)
Turn-OFF Delay Time (Note 2)
Fall Time (Note 2)
15
5
20
15
15
5
35
20
15
5
50
30
ns
-4
50
1
-10
150
0.4
30
30
14
-2
25
200
1
-5
75
0.4
60
60
14
-0.5
5
200
1
V
-3
30
0.4
100
100
14
3.5
C
rss
3.5
pF
V
DS
= 0
mA
V
nA
-40
100
-200
-40
100
-200
nA
V
pA
V
DS
= 20V
I
G
= -1µA, V
DS
= 0
V
GS
= -5V (4393)
V
GS
= -7V (4392)
V
GS
= -12V (4391)
T
A
= 150
o
C
I
G
= 1mA, V
DS
= 0
V
DS
= 20V, I
D
= 1nA
V
DS
= 20V, V
GS
= 0
V
GS
= 0
I
D
= 3mA (4393)
I
D
= 6mA (4392)
I
D
= 12mA (4391)
4392
-100
4393
-100
MIN MAX MIN MAX MIN MAX
UNITS
pA
V
GS
= -20V, V
DS
= 0
T
A
= 150
o
C
TEST CONDITIONS
Ω
V
GS
= 0, I
D
= 1mA
V
GS
= 0, I
D
= 0
V
DS
= 20V, V
GS
= 0
V
GS
= -5V
V
GS
= -7V
V
GS
= -12V
V
DD
= 10V, V
GS(on)
= 0
4391
4392
4393
I
D(on)
12mA
6
3
V
GS(off)
-12V
-7
-5
f = 1MHz
f = 1kHz
NOTES: 1.
Pulse test required, pulse width = 300µs, duty cycle
≤3%.
2.
For design reference only, not 100% tested.
SWITCHING TIMES TEST CIRCUIT
R
L
D
PULSE
IN
1 kΩ
V
IN
SCOPE
51Ω
R
L
=
51Ω
V
DD
1000pF
51Ω
V
OUT
9.6
I
D(ON)
- 51Ω
0010
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
