Direct RDRAM
288-Mbit (512kx18x32s)
Overview
The INFINEON Direct RDRAM is a general purpose high-performance memory device suitable for
use in a broad range of applications including computer memory, graphics, video, and any other
application where high bandwidth and low latency are required.
The 288-Mbit Direct Rambus DRAMs (RDRAM
) are extremely high-speed CMOS DRAMs
organized as 16M words by 18 bits. The use of Rambus Signaling Level (RSL) technology permits
600 MHz to 800 MHz transfer rates while using conventional system and board design
technologies. Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two
bytes (10 ns per sixteen bytes).
The architecture of the Direct RDRAMs allows the highest sustained bandwidth for multiple,
simultaneous randomly addressed memory transactions. The separate control and data buses with
independent row and column control yield over 95% bus efficiency. The Direct RDRAM’s thirty-two
banks support up to four simultaneous transactions.
System oriented features for mobile, graphics and large memory systems include power
management, byte masking, and x18 organization. The two data bits in the x18 organization are
general and can be used for additional storage and bandwidth or for error correction.
Features
• Highest sustained bandwidth per DRAM device
– 1.6 GB/s sustained data transfer rate
– Separate control and data buses for maximized efficiency
– Separate row and column control buses for easy scheduling and highest performance
– 32 banks: four transactions can take place simultaneously at full bandwidth data rates
• Low latency features
– Write buffer to reduce read latency
– 3 precharge mechanisms for controller flexibility
– Interleaved transactions
• Advanced power management:
– Multiple low power states allows flexibility in power consumption versus time to transition to
active state
– Power-down self-refresh
• Organization: 2 Kbyte pages and 32 banks, x18
– x18 organization allows ECC configurations or increased storage/bandwidth
• Uses Rambus Signaling Level (RSL) for up to 800 MHz operation
• The ODF function is allready implemented in this device and will be described in a later version
of this document.
Data Sheet
1
9.01
Direct RDRAM
288-Mbit (512kx18x32s)
0
-84
8C
81
8
R2 10
00
Figure 1
Direct RDRAM CSP Package
The 288-Mbit Direct RDRAMs are offered in a CSP horizontal package suitable for desktop as well
as low-profile add-in card and mobile applications.
Direct RDRAMs operate from a 2.5 V supply.
Table 1
Key Timing Parameters/Part Numbers
I/O Freq.
MHz
600
711
800
800
600
711
800
800
Trac
Part Number
Organization
Normal Package:
16M
×
18
16M
×
18
16M
×
18
16M
×
18
Mirror Package:
53 ns
45 ns
45 ns
40 ns
53 ns
45 ns
45 ns
40 ns
HYB25R288180C-653
HYB25R288180C-745
HYB25R288180C-845
HYB25R288180C-840
HYB25M288180C-653
HYB25M288180C-745
HYB25M288180C-845
HYB25M288180C-840
16M
×
18
16M
×
18
16M
×
18
16M
×
18
Data Sheet
2
9.01
Direct RDRAM
288-Mbit (512kx18x32s)
Pinouts and Definitions
(9x8)
Center-Bonded Devices
These tables shows the pin assignments of the 9x8 center-bonded RDRAM package. The top
table is for the normal package, and bottom table is for the mirrored package. The mechanical
dimensions of this package are shown in the last section.
Table 2: 9x8 Center-Bonded Device (top view for normal package)
10
9
8
7
6
5
4
3
2
1
Top view for
normal
package
NC
NC
DQA7
GND
NC
CMD
DQA4
VDD
DQA5
CFM
GND
DQA2
CFMN
GNDa
VDDa
RQ5
VDD
RQ6
RQ3
GND
RQ2
DQB0
VDD
DQB1
DQB4
VDD
DQB5
DQB7
GND
SIO1
NC
NC
NC
NC
SCK
VCMOS
DQA6
GND
DQA3
DQA1
VDD
DQA0
VREF
GND
CTMN
RQ7
GND
CTM
RQ1
VDD
RQ4
DQB2
GND
RQ0
DQB6
GND
DQB3
SIO0
VCMOS
DQB8
NC
NC
NC
NC
A
B
DQA8
NC
C
D
E
F
G
H
J
K
L
M
N
Table 3: 9x8 Center-Bonded Device (top view for mirrored package)
10
9
8
7
6
5
4
3
2
1
Top view for
m irrored
package
NC
NC
DQA8
VCMOS
NC
SCK
DQA3
GND
DQA6
DQA0
VDD
DQA1
CTMN
GND
VREF
CTM
GND
RQ7
RQ4
VDD
RQ1
RQ0
GND
DQB2
DQB3
GND
DQB6
DQB8
VCMOS
SIO0
NC
NC
NC
NC
CMD
GND
DQA5
VDD
DQA4
DQA2
GND
CFM
VDDa
GNDa
CFMN
RQ6
VDD
RQ5
RQ2
GND
RQ3
DQB1
VDD
DQB0
DQB5
VDD
DQB4
SIO1
GND
DQB7
NC
NC
NC
NC
A
B
DQA7
NC
C
D
E
F
G
H
J
K
L
M
N
Data Sheet
3
9.01
Direct RDRAM
288-Mbit (512kx18x32s)
Table 4
Signal
SIO1,SIO0
I/O
I/O
Type
CMOS
1)
# Pins
Center
2
Description
Serial input/output. Pins for reading from and writing to
the control registers using a serial access protocol.
Also used for power management.
Command input. Pins used in conjunction with SIO0
and SIO1 for reading from and writing to the control
registers. Also used for power management.
Serial clock input. Clock source used for reading from
and writing to the control registers.
Supply voltage for the RDRAM core and interface logic.
Supply voltage for the RDRAM analog circuitry.
Supply voltage for CMOS input/output pins.
Ground reference for RDRAM core and interface.
Ground reference for RDRAM analog circuitry.
Data byte A. Nine pins which carry a byte of read or
write data between the Channel and the RDRAM.
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Positive polarity.
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Negative polarity
Logic threshold reference voltage for RSL signals
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Negative polarity.
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Positive polarity.
Row access control. Three pins containing control and
address information for row accesses.
Column access control. Five pins containing control
and address information for column accesses.
Data byte B. Nine pins which carry a byte of read or
write data between the Channel and the RDRAM.
CMD
I
CMOS
1)
1
SCK
I
CMOS
1)
1
6
1
2
9
1
9
1
1
1
V
DD
V
DDa
V
CMOS
GND
GNDa
DQA8 … DQA0
CFM
CFMN
–
–
–
–
–
I/O
I
I
–
–
–
–
–
RSL
2)
RSL
2)
RSL
2)
V
REF
CTMN
CTM
I
I
RSL
2)
RSL
2)
RSL
2)
RSL
2)
RSL
2)
1
1
3
5
9
54
RQ7 … RQ5 or
I
ROW2 … ROW0
RQ4 … RQ0 or
COL4 … COL0
DQB8 … DQB0
I
I/O
Total pin count per package
1)
2)
–
All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
Data Sheet
4
9.01
Direct RDRAM
288-Mbit (512kx18x32s)
DQB8..DQB0
9
RQ7..RQ5 or
ROW2..ROW0
3
RCLK
1:8 Demux
CTM CTMN
SCK,CMD SIO0,SIO1
2
2
CFM CFMN
RQ4..RQ0 or
COL4..COL0
5
DQA8..DQA0
9
RCLK
1:8 Demux
TCLK
RCLK
Control Registers
6
REFR
Power Modes
Packet Decode
ROWR
ROWA
11
5
5
9
ROP DR
AV
Match
COLX
5
5
DX
Packet Decode
COLC
5
5
5
7
BX COP DC
S
Match
8
C
COLM
8
BR
R
DEVID
XOP
M
BC
MB MA
Mux
Row Decode
Match
XOP Decode
DM
Write
Buffer
Mux
Mux
PRER
ACT
Sense Amp
64x72
SAmp SAmp SAmp
PREX
Column Decode & Mask
DRAM Core
64x72 512x128x144
0
Bank 0
0/1
64x72
72
SAmp SAmp SAmp
PREC
RD, WR
0
Internal DQB Data Path
72
72
Internal DQA Data Path
0/1
Bank 1
1/2
72
1/2
RCLK
9
9
•••
Bank 2
•••
9
•••
9
RCLK
SAmp SAmp SAmp
14/15 13/14
Bank 13
Bank 14
Bank 15
13/14 14/15
SAmp SAmp SAmp
Write Buffer
Write Buffer
1:8 Demux
1:8 Demux
9
9
15
15
SAmp SAmp SAmp
SAmp SAmp SAmp
16
16
17/18 16/17
Bank 16
Bank 17
Bank 18
•••
16/17 17/18
TCLK
9
9
TCLK
•••
8:1 Mux
•••
8:1 Mux
9
9
SAmp SAmp SAmp
30/31 29/30
Bank 29
Bank 30
Bank 31
29/30 30/31
SAmp SAmp SAmp
31
31
Figure 2
288-MBit Direct RDRAM Block Diagram
Data Sheet
5
9.01
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