SN54ACT374, SN74ACT374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS539F − OCTOBER 1995 − REVISED NOVEMBER 2002
D
D
D
D
4.5-V to 5.5-V V
CC
Operation
Inputs Accept Voltages to 5.5 V
Max t
pd
of 10 ns at 5 V
Inputs Are TTL-Voltage Compatible
SN54ACT374 . . . J OR W PACKAGE
SN74ACT374 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
description/ordering information
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight flip-flops of the ’ACT374 devices are
D-type edge-triggered flip-flops. On the positive
transition of the clock (CLK) input, the Q outputs
are set to the logic levels set up at the data (D)
inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
the increased drive provide the capability to drive
bus lines in bus-organized systems without need
for interface or pullup components.
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
SN54ACT374 . . . FK PACKAGE
(TOP VIEW)
1D
1Q
OE
V
CC
2D
2Q
3Q
3D
4D
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
8Q
8D
7D
7Q
6Q
6D
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
T
A
PDIP − N
SOIC − DW
−40°C to 85°C
40°C
SOP − NS
SSOP − DB
TSSOP − PW
CDIP − J
−55°C to 125°C
†
PACKAGE
†
Tube
Tube
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tube
Tube
Tube
ORDERABLE
PART NUMBER
SN74ACT374N
SN74ACT374DW
SN74ACT374DWR
SN74ACT374NSR
SN74ACT374DBR
SN74ACT374PWR
SNJ54ACT374J
SNJ54ACT374W
SNJ54ACT374FK
CFP − W
LCCC − FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
4Q
GND
CLK
5Q
5D
TOP-SIDE
MARKING
SN74ACT374N
ACT374
ACT374
AD374
AD374
SNJ54ACT374J
SNJ54ACT374W
SNJ54ACT374FK
1
SN54ACT374, SN74ACT374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS539F − OCTOBER 1995 − REVISED NOVEMBER 2002
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
L
L
L
H
CLK
↑
↑
H or L
X
D
H
L
X
X
OUTPUT
Q
H
L
Q
0
Z
logic diagram (positive logic)
OE
CLK
1
11
C1
1D
3
1D
2
1Q
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Output voltage range, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±200
mA
Package thermal impedance,
θ
JA
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
†
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54ACT374, SN74ACT374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS539F − OCTOBER 1995 − REVISED NOVEMBER 2002
recommended operating conditions (see Note 3)
SN54ACT374
MIN
V
CC
V
IH
V
IL
V
I
V
O
I
OH
I
OL
Δt/Δv
T
A
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
−55
0
0
4.5
2
0.8
V
CC
V
CC
−24
24
8
125
−40
0
0
MAX
5.5
SN74ACT374
MIN
4.5
2
0.8
V
CC
V
CC
−24
24
8
85
MAX
5.5
UNIT
V
V
V
V
V
mA
mA
ns/V
°C
NOTE 3: All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
I
OH
= −50
μA
50 A
V
OH
I
OH
= −24 mA
24
I
OH
= −50 mA
†
I
OH
= −75 mA
†
I
OL
= 50
μA
A
V
OL
I
OL
= 24 mA
I
OL
= 50 mA
†
I
OL
= 75 mA
†
I
OZ
I
I
I
CC
ΔI
CC‡
C
i
†
‡
V
CC
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
T
A
= 25°C
MIN
4.4
5.4
3.86
4.86
TYP
4.49
5.49
MAX
SN54ACT374
MIN
4.4
5.4
3.7
4.7
3.85
MAX
SN74ACT374
MIN
4.4
5.4
3.76
4.76
3.85
V
MAX
UNIT
0.1
0.1
0.36
0.36
0.1
0.1
0.44
0.5
1.65
0.1
0.1
0.44
0.44
1.65
V
V
O
= V
CC
or GND
V
I
= V
CC
or GND
V
I
= V
CC
or GND,
I
O
= 0
One input at 3.4 V,
Other inputs at GND or V
CC
V
I
= V
CC
or GND
±0.25
±0.1
4
0.6
4.5
±5
±1
80
1.6
±2.5
±1
40
1.5
μA
μA
μA
mA
pF
5.5 V
5.5 V
5V
Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or V
CC
.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SN54ACT374, SN74ACT374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS539F − OCTOBER 1995 − REVISED NOVEMBER 2002
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
±
0.5 V
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
MIN
f
clock
t
w
t
su
t
h
Clock frequency
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
5
5
1.5
MAX
100
5
5.5
1.5
SN54ACT374
MIN
MAX
70
5
5.5
1.5
SN74ACT374
MIN
MAX
90
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
CLK
OE
OE
Q
Q
Q
FROM
(INPUT)
TO
(OUTPUT)
T
A
= 25°C
MIN
100
2
2
2
1.5
1.5
1.5
TYP
160
8.5
8
8
8
8.5
7
10
9.5
9.5
9
11.5
8.5
MAX
SN54ACT374
MIN
70
1.5
1.5
1.5
1.5
1.5
1.5
12
11.5
11.5
11.5
13
11
MAX
SN74ACT374
MIN
90
2
1.5
1.5
1.5
1
1
11.5
11
10.5
10.5
12.5
10
ns
ns
ns
MAX
UNIT
MHz
operating characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER
C
pd
Power dissipation capacitance
TEST CONDITIONS
C
L
= 50 pF,
f = 1 MHz
TYP
40
UNIT
pF
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54ACT374, SN74ACT374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS539F − OCTOBER 1995 − REVISED NOVEMBER 2002
PARAMETER MEASUREMENT INFORMATION
2
×
V
CC
From Output
Under Test
C
L
= 50 pF
(see Note A)
500
Ω
S1
Open
TEST
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
S1
Open
2
×
V
CC
Open
500
Ω
3V
Timing Input
LOAD CIRCUIT
t
su
t
w
3V
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
t
PZL
3V
Input
1.5 V
t
PLH
Output
50% V
CC
VOLTAGE WAVEFORMS
1.5 V
0V
t
PHL
V
OH
50% V
CC
V
OL
Output
Waveform 2
S1 at Open
(see Note B)
Output
Waveform 1
S1 at 2
×
V
CC
(see Note B)
t
PZH
50% V
CC
VOLTAGE WAVEFORMS
50% V
CC
3V
1.5 V
1.5 V
0V
t
PLZ
≈V
CC
V
OL
+ 0.3 V
t
PHZ
V
OH
− 0.3 V
V
OH
≈0
V
V
OL
Data Input
1.5 V
1.5 V
t
h
0V
3V
1.5 V
0V
VOLTAGE WAVEFORMS
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
1 MHz, Z
O
= 50
Ω,
t
r
≤
2.5 ns, t
f
≤
2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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