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Freescale Semiconductor
Technical Data
MPC8245EC
Rev. 10, 08/2007
MPC8245 Integrated Processor
Hardware Specifications
The MPC8245 combines a PowerPC™ MPC603e processor
core built on Power Architecture™ technology with a PCI
bridge so that system designers can rapidly design systems
using peripherals designed for PCI and the other standard
interfaces. Also, a high-performance memory controller
supports various types of ROM and SDRAM. The MPC8245
is the second of a family of products that provide
system-level support for industry-standard interfaces with an
MPC603e processor core.
This hardware specification describes pertinent electrical
and physical characteristics of the MPC8245. For functional
characteristics of the processor, refer to the
MPC8245
Integrated Processor Reference Manual
(MPC8245UM).
For published errata or updates to this document, visit the
website listed on the back cover of the document.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical and Thermal Characteristics . . . . . . . . . . . . 5
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 31
PLL Configurations . . . . . . . . . . . . . . . . . . . . . . . . . 39
System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Document Revision History . . . . . . . . . . . . . . . . . . . 56
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 62
1
Overview
The MPC8245 integrated processor is composed of a
peripheral logic block and a 32-bit superscalar MPC603e
core, as shown in
Figure 1.
© Freescale Semiconductor, Inc., 2001–2007. All rights reserved.
Overview
MPC8245
Additional Features:
• Prog I/O with Watchpoint
• JTAG/COP Interface
• Power Management
Processor Core Block
Processor
PLL
(64-Bit) Two-Instruction Fetch
Branch
Processing
Instruction Unit
Unit
(BPU)
(64-Bit) Two-Instruction Dispatch
System
Register
Unit
(SRU)
Integer
Unit
(IU)
Load/Store
Unit
(LSU)
Floating-
Point
Unit
(FPU)
64-Bit
Data
MMU
16-Kbyte
Data
Cache
Instruction
MMU
16-Kbyte
Instruction
Cache
Peripheral Logic Bus
Peripheral Logic Block
Message
Unit
(with I
2
O)
DMA
Controller
Address
(32-Bit)
Central
Control
Unit
Performance
Monitor
I C
2
Data (64-Bit)
Data Path
ECC Controller
Data Bus
(32- or 64-Bit)
with 8-Bit Parity
or ECC
Memory/ROM/
PortX Control/Address
Memory
Controller
I C
Controller
PIC
Interrupt
Controller/
Timers
DUART
2
SDRAM_SYNC_IN
DLL
SDRAM Clocks
PCI_SYNC_IN
5 IRQs/
16 Serial
Interrupts
Peripheral Logic
PLL
Configuration
Registers
PCI Bus
Interface Unit
Address
Translator
PCI
Arbiter
Watchpoint
Facility
Fanout
Buffers
OSC_IN
PCI Bus
Clocks
Five
32-Bit
PCI Interface Request/Grant Pairs
Figure 1. MPC8245 Block Diagram
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
2
Freescale Semiconductor
Features
The peripheral logic integrates a PCI bridge, dual universal asynchronous receiver/transmitter (DUART),
memory controller, DMA controller, PIC interrupt controller, a message unit (and I
2
O interface), and an
I
2
C controller. The processor core is a full-featured, high-performance processor with floating-point
support, memory management, a 16-Kbyte instruction cache, a 16-Kbyte data cache, and power
management features. The integration reduces the overall packaging requirements and the number of
discrete devices required for an embedded system.
An internal peripheral logic bus interfaces the processor core to the peripheral logic. The core can operate
at a variety of frequencies, allowing the designer to trade off performance for power consumption. The
processor core is clocked from a separate PLL that is referenced to the peripheral logic PLL. This allows
the microprocessor and the peripheral logic block to operate at different frequencies while maintaining a
synchronous bus interface. The interface uses a 64- or 32-bit data bus (depending on memory data bus
width) and a 32-bit address bus along with control signals that enable the interface between the processor
and peripheral logic to be optimized for performance. PCI accesses to the MPC8245 memory space are
passed to the processor bus for snooping when snoop mode is enabled.
The general-purpose processor core and peripheral logic serve a variety of embedded applications. The
MPC8245 can be used as either a PCI host or PCI agent controller.
2
Features
Major features of the MPC8245 are as follows:
• Processor core
— High-performance, superscalar processor core
— Integer unit (IU), floating-point unit (FPU) (software enabled or disabled), load/store unit
(LSU), system register unit (SRU), and branch processing unit (BPU)
— 16-Kbyte instruction cache
— 16-Kbyte data cache
— Lockable L1 caches—Entire cache or on a per-way basis up to three of four ways
— Dynamic power management: 60x nap, doze, and sleep modes
• Peripheral logic
— Peripheral logic bus
– Various operating frequencies and bus divider ratios
– 32-bit address bus, 64-bit data bus
– Full memory coherency
– Decoupled address and data buses for pipelining of peripheral logic bus accesses
– Store gathering on peripheral logic bus-to-PCI writes
— Memory interface
– Up to 2 Gbytes of SDRAM memory
– High-bandwidth data bus (32- or 64-bit) to SDRAM
– Programmable timing supporting SDRAM
– One to eight banks of 16-, 64-, 128-, 256-, or 512-Mbit memory devices
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
3
Features
—
—
—
—
Write buffering for PCI and processor accesses
Normal parity, read-modify-write (RMW), or ECC
Data-path buffering between memory interface and processor
Low-voltage TTL logic (LVTTL) interfaces
272 Mbytes of base and extended ROM/Flash/PortX space
Base ROM space for 8-bit data path or same size as the SDRAM data path (32- or 64-bit)
Extended ROM space for 8-, 16-, 32-bit gathering data path, 32- or 64-bit (wide) data path
PortX: 8-, 16-, 32-, or 64-bit general-purpose I/O port using ROM controller interface with
programmable address strobe timing, data ready input signal (DRDY), and 4 chip selects
32-bit PCI interface
– Operates up to 66 MHz
– PCI 2.2-compatible
– PCI 5.0-V tolerance
– Dual address cycle (DAC) for 64-bit PCI addressing (master only)
– Accesses to PCI memory, I/O, and configuration spaces
– Selectable big- or little-endian operation
– Store gathering of processor-to-PCI write and PCI-to-memory write accesses
– Memory prefetching of PCI read accesses
– Selectable hardware-enforced coherency
– PCI bus arbitration unit (five request/grant pairs)
– PCI agent mode capability
– Address translation with two inbound and outbound units (ATU)
– Internal configuration registers accessible from PCI
Two-channel integrated DMA controller (writes to ROM/PortX not supported)
– Direct mode or chaining mode (automatic linking of DMA transfers)
– Scatter gathering—Read or write discontinuous memory
– 64-byte transfer queue per channel
– Interrupt on completed segment, chain, and error
– Local-to-local memory
– PCI-to-PCI memory
– Local-to-PCI memory
– PCI memory-to-local memory
Message unit
– Two doorbell registers
– Two inbound and two outbound messaging registers
– I
2
O message interface
I
2
C controller with full master/slave support that accepts broadcast messages
–
–
–
–
–
–
–
–
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
4
Freescale Semiconductor
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