DISCRETE SEMICONDUCTORS
DATA SHEET
book, halfpage
M3D087
BSP89
N-channel enhancement mode
vertical D-MOS transistor
Product specification
Supersedes data of 1997 Jun 23
2001 May 18
Philips Semiconductors
Product specification
N-channel enhancement mode
vertical D-MOS transistor
FEATURES
•
Direct interface to C-MOS, TTL,
etc.
•
High-speed switching
•
No secondary breakdown.
DESCRIPTION
N-channel enhancement mode
vertical D-MOS transistor in a
SOT223 package, intended for use as
a surface-mounted device in line
current interrupters in telephone sets
and for application in relay, high
speed and line transformer drivers.
PINNING - SOT223
1
2
3
MAM109
BSP89
QUICK REFERENCE DATA
SYMBOL
V
DS
V
GSth
I
D
R
DSon
PARAMETER
drain-source voltage (DC)
gate-source threshold voltage
drain current (DC)
drain-source on-state resistance
2
375
5
MAX.
240
UNIT
V
V
mA
Ω
handbook, halfpage
4
d
g
s
PIN
1
2
3
4
gate
drain
DESCRIPTION
Code: BSP89
Top view
source
drain
Fig.1 Simplified outline (SOT223) and symbol.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
V
DS
V
GSO
I
D
I
DM
P
tot
T
stg
T
j
Note
1. Transistor mounted on an epoxy printed circuit board, 40 x 40 x 1.5 mm, mounting pad for the drain tab minimum
6 cm
2
.
PARAMETER
drain-source voltage (DC)
gate-source voltage (DC)
drain current (DC)
peak drain current
total power dissipation
storage temperature
junction temperature
T
amb
≤
25
°C;
note 1
open drain
CONDITIONS
MIN.
−
−
−
−
−
−55
−
MAX.
240
±20
375
1.5
1.5
+150
150
UNIT
V
V
mA
A
W
°C
°C
2001 May 18
2
Philips Semiconductors
Product specification
N-channel enhancement mode
vertical D-MOS transistor
THERMAL CHARACTERISTICS
SYMBOL
R
th j-a
Note
PARAMETER
thermal resistance from junction to ambient; note 1
VALUE
83.3
BSP89
UNIT
K/W
1. Transistor mounted on an epoxy printed circuit board, 40 x 40 x 1.5 mm, mounting pad for the drain tab minimum
6 cm
2
.
CHARACTERISTICS
T
j
= 25
°C
unless otherwise specified.
SYMBOL
V
(BR)DSS
I
DSS
I
GSS
V
GSth
R
DSon
Y
fs
C
iss
C
oss
C
rss
t
on
t
off
PARAMETER
drain-source breakdown voltage
drain-source leakage current
gate-source leakage current
gate-source threshold voltage
drain-source on-state resistance
transfer admittance
input capacitance
output capacitance
reverse transfer capacitance
CONDITIONS
I
D
= 10
µA;
V
GS
= 0
V
DS
= 60 V; V
GS
= 0
V
GS
=
±20
V; V
DS
= 0
I
D
= 1 mA; V
GS
= V
DS
I
D
= 340 mA; V
GS
= 10 V
I
D
= 340 mA; V
GS
= 4.5 V
I
D
= 340 mA; V
DS
= 25 V
V
DS
= 25 V; V
GS
= 0; f = 1 MHz
V
DS
= 25 V; V
GS
= 0; f = 1 MHz
V
DS
= 25 V; V
GS
= 0; f = 1 MHz
I
D
= 250 mA; V
DD
= 50 V;
V
GS
= 0 to 10 V
I
D
= 250 mA; V
DD
= 50 V;
V
GS
= 0 to 10 V
MIN.
240
−
−
0.8
−
−
140
−
−
−
−
−
TYP.
−
−
−
−
2.8
−
600
100
20
10
MAX.
−
200
100
2
5
7.5
−
120
30
15
UNIT
V
nA
nA
V
Ω
Ω
mS
pF
pF
pF
Switching times (see Figs
3
and
4)
turn-on time
turn-off time
6
47
10
60
ns
ns
2001 May 18
3
Philips Semiconductors
Product specification
N-channel enhancement mode
vertical D-MOS transistor
BSP89
handbook, halfpage
2
MBB693
Ptot
(W)
1.6
handbook, halfpage
VDD = 50 V
1.2
0.8
10 V
0.4
0V
ID
50
Ω
MBB691
0
0
50
100
200
150
Tamb (°C)
Fig.2 Power derating curve.
Fig.3 Switching times test circuit.
handbook, halfpage
90 %
INPUT
10 %
90 %
OUTPUT
10 %
ton
toff
MBB692
Fig.4 Input and output waveforms.
2001 May 18
4
Philips Semiconductors
Product specification
N-channel enhancement mode
vertical D-MOS transistor
PACKAGE OUTLINE
Plastic surface mounted package; collector pad for good heat transfer; 4 leads
BSP89
SOT223
D
B
E
A
X
c
y
H
E
b
1
v
M
A
4
Q
A
A
1
1
e
1
e
2
b
p
3
w
M
B
detail X
L
p
0
2
scale
4 mm
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A
1.8
1.5
A
1
0.10
0.01
b
p
0.80
0.60
b
1
3.1
2.9
c
0.32
0.22
D
6.7
6.3
E
3.7
3.3
e
4.6
e
1
2.3
H
E
7.3
6.7
L
p
1.1
0.7
Q
0.95
0.85
v
0.2
w
0.1
y
0.1
OUTLINE
VERSION
SOT223
REFERENCES
IEC
JEDEC
EIAJ
SC-73
EUROPEAN
PROJECTION
ISSUE DATE
97-02-28
99-09-13
2001 May 18
5
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