M21250/M21251/M21252
Quad-Channel CDR/Reclocker (42 Mbps - 3.2 Gbps)
The M21250, M21251, and M21252 (M2125x) devices are high-performance quad channel retimers optimized for
telecom, datacom, and digital video applications. Each channel of the CDR/reclocker array includes an
independent multi-rate CDR/reclocker, allowing maximum flexibility in system design. Signal conditioning features
of the M2125x include input equalization and output pre-emphasis to compensate for lossy PCB traces and
backplane connectors. A built-in frequency synthesizer allows each channel of the device to operate at a different
data rate simultaneously while operating from a single reference clock. The M2125x can be controlled through
hardwired pins or via a 2-wire or 4-wire serial programming interface. The serial programming interface allows
users to have complete control of the device features. The M2125x devices support JTAG external boundary scan
which includes all of the high-speed I/O as well as the digital I/O.
Features
• Four independent CDR/reclockers (CDR/RCLKs) SMPTE, DVB-ASI
compliant
• Integrated loop filter and terminations
• Serial control or hardwired control, JTAG boundary scan
• Low power consumption of 400 mW (1 channel active)
• Built-in pattern generator and receiver with JTAG support for
module and system testing (PRBS, 8b/10b, Fibre Channel, User
Programmable patterns)
• User Selectable Input Equalization and Pre-Emphasis for backplane
ISI reduction
• Multirate support (42 Mbps - 3.2 Gbps)
• Differential outputs for recovered clock and retimed data
Applications
•
•
•
•
•
•
•
•
•
3G/HD/SD-SDI Routing Switchers
3G/HD/SD-SDI Video Transport Systems
3G/HD/SD-SDI Distribution Amplifiers
Backplane Reach Extension
SONET Systems and Modules
10GBASE-CX4 Systems
Gigabit Ethernet Systems
SAS/S-ATA/S-ATA2 Systems
PCI Express
Standards Compliance
•
•
•
•
SMPTE 292M
SMPTE 259M
SMPTE 344M
SMPTE 424M
Functional Block Diagram
CTRL_Mode[1:0]
Out_Mode[1:0]
xJTAG_En
Multi-function Pin Array
Serial Interface
/Hardwired Mode
Din0P/N
JTAG
Voltage
Regulator
Cout0P/N
Selectable CML, LVDS
BIST Transmitter Mux
xRegu_En
xLOA[3:0]
xLOL[3:0]
MF[11:0]
xRST
Reclocker Array
VddT0/1
Din1P/N
Cout1P/N
Output Buffer
Input Buffer
Cout2P/N
Cout3P/N
Dout0P/N
Dout1P/N
Dout2P/N
Dout3P/N
Din2P/N
VddT2/3
Din3P/N
BIST Tx
(PRBS &
8b/10)
BIST Rx
(PRBS &
8b/10)
2125x-DSH-001-H
Mindspeed Technologies
®
Mindspeed Proprietary and Confidential
RefClkP/N
BIST Rx Mux
March 2009
Ordering Information
Part Number
M21250 Quad Multi-rate CDR/Reclocker (42–3200 Mbps)
M21251 Quad Multi-rate CDR/Reclocker (42–1600 Mbps)
M21252 Quad Multi-rate CDR/Reclocker (42–540 Mbps)
M21250 Quad Multi-rate CDR/Reclocker (42–3200 Mbps)
M21251 Quad Multi-rate CDR/Reclocker (42–1600 Mbps)
M21252 Quad Multi-rate CDR/Reclocker (42–540 Mbps)
Ordering Part Number
M21250-12
DS-M21251-21
DS-M21252-21
M21250G-12*
DS-M21251G-21*
DS-M21252G-21*
Package
72-terminal, 10mm, QFN
72-terminal, 10mm, QFN
72-terminal, 10mm, QFN
72-terminal, 10mm, QFN, RoHS compliant package
72-terminal, 10mm, QFN, RoHS compliant package
72-terminal, 10mm, QFN, RoHS compliant package
* The letter “G” designator after the part number indicates that the device is RoHS-compliant. The RoHS-compliant devices are backwards
compatible with 225°C reflow profiles.
Refer to www.mindspeed.com for additional information.
Revision History
Revision
H
Date
March 2009
Comments
- Added 3G support.
- Revised xCS timing in
Figure 1-5
and
Figure 1-6.
- Added SD HD, and 3G parameters to
Table 1-12
and Pin 24 default in
Table 1-21.
- Added Note 4 in
Table 2-2.
- Revised Bit 5 description in
Table 3-33.
- Added SMPTE 424M in standards compliance list.
- Revised bit 5:4 description in
Table 3-31.
- Added additional register details in
Section 3.0.
- Added support for Telecom and Datacom applications.
- Revised maximum input termination to
VddT
specification,
Table 2-5.
- Added clock output differential medium swing specification,
Table 2-6.
- Reformatted register tables.
- Updated ordering part numbers.
- Adjusted temperature range to -40°C to +85°C
- Changed ESD rating for HBM testing to 350V.
- Included details for operation at data rates above 3.0 Gbps.
- References to LVPECL output mode removed. Inputs can be AC-coupled to LVPECL.
- Adjusted temperature range to 0
°
C to +70
°
C from -40
°
C to +85
°
C.
- Added RoHS packaging options.
- Input sensitivity change from 50 mVpp to 100 mVpp.
- Updated ARD description.
- Updated device register tables.
Revision B.
Original release.
G
May 2008
F
June 2006
E
August 2005
D
C
July 2005
January 2005
B
A
April 2004
October 2003
2125x-DSH-001-H
Mindspeed Technologies
®
Mindspeed Proprietary and Confidential
ii
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
1.0
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Detailed Feature Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2.1
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2.2
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2.3
Internal Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2.4
High-Speed Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2.5
CDR/Reclocker Reference Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.2.6
Multifunction Pins Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.2.7
Multifunction Pins Defined for Hardwired Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.2.8
Multi-function Pins: Four-Wire Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.2.9
Two-Wire Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.2.10 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.2.11 Input Deterministic Jitter Attenuators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.2.12 Output Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.2.13 CDR/RCLK Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.2.14 General CDR/RCLK Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.2.15 Multi-Rate CDR Data-Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.2.16 Frequency Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.2.17 CDR/Reclocker Data Rate Programming (3G/HD/SD-SDI Video Rates Only) . . . . . . . . . . . . . . . . . . . . . .17
1.2.18 Ambient Temperature Range Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.2.19 Loss of Activity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.2.20 Built-In Self Test (BIST) Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.2.21 BIST Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.2.22 BIST Receiver (BIST Rx) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.2.23 BIST Transmitter (BIST Tx) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.2.24 Junction Temperature Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.2.25 IC Identification / Revision Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.3
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Table of Contents
2.0
Product Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Input/Output Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
High-Speed Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Package Drawings and Surface Mount Assembly Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
PCB High-Speed Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Auto Rate Detect (ARD) for HD/SD-SDI Digital Video Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
3.0
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.1
Global Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.1.1
00h:Global Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.1.2
04h: External Reference Frequency Divider Control (RFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.1.3
05h:Master IC Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.1.4
06h:IC Electronic Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.1.5
07h:IC Revision Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.1.6
10h:Built In Self-Test (BIST) Receiver Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.1.7
11h:Built In Self-Test (BIST) Receiver Main Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
3.1.8
12h:Built In Self-Test (BIST) Receiver Bit Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
3.1.9
14h:Built In Self-Test (BIST) Transmitter Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3.1.10 15h:Built In Self-Test (BIST) Transmitter Main Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3.1.11 17h:Built In Self-Test (BIST) Transmitter PLL Loss of Lock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .54
3.1.12 18h:Built In Self-Test (BIST) Transmitter PLL Control Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
3.1.13 19h:Built In Self-Test (BIST) Transmitter PLL Control Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
3.1.14 1Ah:Built In Self-Test (BIST) Transmitter PLL Control Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
3.1.15 1Bh:Built In Self-Test (BIST) Transmitter 20 bit User Programmable Pattern . . . . . . . . . . . . . . . . . . . . .56
3.1.16 1Ch:Built In Self-Test (BIST) Transmitter 16/20 bit User Programmable Pattern. . . . . . . . . . . . . . . . . . .57
3.1.17 1Dh:Built In Self-Test (BIST) Transmitter 16/20 bit User Programmable Pattern. . . . . . . . . . . . . . . . . . .57
3.1.18 1Fh:Built In Self-Test (BIST) Transmitter Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
3.1.19 20h:Internal Junction Temperature Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
3.1.20 21h:Internal Junction Temperature Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
3.1.21 30h:CDR/RCLK Loss of Lock Register Alarm Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
3.1.22 31h:Loss of Activity Register Alarm Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
3.1.23 32h:VCO Trim Alarm Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Individual Channel/CDR/RCLK Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
M0h:CDR N Control Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
M1h:CDR/RCLK N Control Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
M2h:CDR/RCLK N Control Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
M3h:Output Buffer Control for CDR/RCLK N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
M4h:Output Buffer Pre-Emphasis Control for Output N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
M5h:Input Equalization Control for Output N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
M6h:CDR/RCLK N Loop Bandwidth and Data Sampling Point Adjust. . . . . . . . . . . . . . . . . . . . . . . . . . . .64
M9h:CDR/RCLK N LOL Window Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
MAh: Jitter Reduction Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
3.2
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®
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Table of Contents
4.0
Appendices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.1
4.2
Glossary of Terms/Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
4.2.1
4.2.2
External . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Mindspeed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
2125x-DSH-001-H
Mindspeed Technologies
®
Mindspeed Proprietary and Confidential
v