ASAHI KASEI
[AK5393]
AK5393
Enhanced Dual Bit
∆Σ
96kHz 24-Bit ADC
GENERAL DESCRIPTION
The AK5393 is a 24bit, 128x oversampling 2ch A/D Converter for professional digital audio systems. The
modulator in the AK5393 uses the new developed Enhanced Dual Bit architecture. This new architecture
achieves the wide dynamic range, while keeping much the same superior distortion characteristics as
conventional Single Bit way. The AK5393 performs 117dB dynamic range, so the device is suitable for
professional studio equipment such as digital mixer, digital VTR etc.
FEATURES
p
Enhanced Dual Bit ADC
p
Sampling Rate: 1kHz~108kHz
p
Full Differential Inputs
p
S/(N+D): 105dB
p
DR: 117dB
p
S/N: 117dB
p
High Performance Linear Phase Digital Anti-Alias filter
•
Passband: 0~21.768kHz(@fs=48kHz)
•
Ripple: 0.001dB
•
Stopband: 110dB
p
Digital HPF & Offset Calibration for Offset Cancel
p
Power Supply: 5V±5%(Analog), 3~5.25V(Digital)
p
Power Dissipation: 470mW
p
Package: 28pin SOP
p
AK5392 Pin compatible
SMODE1 SMODE2
12
VREFL
GNDL
VCOML
AINL+
AINL-
ZCAL
AINR+
AINR-
VCOMR
VREFR
GNDR
1
2
3
4
5
6
25
24
26
28
27
23
VA
11
SCLK
14
LRCK
13
FSYNC
16
15
SDATA
Voltage
Reference
Serial Output
Interface
Delta-Sigma
Modulator
Delta-Sigma
Modulator
Voltage
Reference
22
AGND
21
BGND
Decimation
Filter
Decimation
Filter
HPF
19
HPFE
17
MCLK
DFS
HPF
18
Controller
9
CAL
10
RST
Calibration
SRAM
7
VD
8
DGND
M0038-E-04
-1-
2000/4
ASAHI KASEI
n
Ordering Guide
AK5393-VS
AKD5393
–10 ~ +70°C
28pin SOP
AK5393 Evaluation Board
[AK5393]
n
Pin Layout
VREFL
GNDL
VCOML
AINL+
AINL-
ZCAL
VD
DGND
CAL
RST
SMODE2
SMODE1
LRCK
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
VREFR
GNDR
VCOMR
AINR+
AINR-
Top
View
23
22
21
20
19
18
17
16
15
VA
AGND
BGND
TEST
HPFE
DFS
MCLK
FSYNC
SDATA
n
Compatibility with AK5392
AK5392
Pin 18
fs (max)
MCLK (DFS ="L"@fs=48kHz)
MCLK (DFS ="H"@fs=96kHz)
CMODE
54kHz
256fs/384fs
N/A
AK5393
DFS
108kHz
256fs
128fs
M0038-E-04
-2-
2000/4
ASAHI KASEI
[AK5393]
PIN/FUNCTION
No.
1
Pin Name
VREFL
I/O
O
Function
Lch Reference Voltage Pin, 3.75V
Normally connected to GNDL with a 10µF electrolytic capacitor and
a 0.1µF ceramic capacitor.
Lch Reference Ground Pin, 0V
Lch Common Voltage Pin, 2.75V
Lch Analog positive input Pin
Lch Analog negative input Pin
Zero Calibration Control Pin
This pin controls the calibration reference signal.
"L" :VCOML and VCOMR
"H" : Analog Input Pins (AINL±, AINR±)
Digital Power Supply Pin, 3.3V
Digital Ground Pin, 0V
Calibration Active Signal Pin
"H" means the offset calibration cycle is in progress. Offset calibration starts
when RST goes "H". CAL goes "L" after 8704 LRCK cycles for DFS="L",
17408 LRCK cycles for DFS ="H".
Reset Pin
When "L", Digital section is powered-down. Upon returning "H", an
offset calibration cycle is started. An offset calibration cycle should always
be initiated after power-up.
Serial Interface Mode Select Pin
MSB first, 2's compliment.
SMODE2 SMODE1
MODE
LRCK
L
L
Slave mode : MSB justified
: H/L
2
L
H
Master mode : Similar to I S
: H/L
2
H
L
Slave mode : I S
: L/H
2
H
H
Master mode : I S
: L/H
Left/Right Channel Select Clock Pin
LRCK goes "H" at SMODE2="L" and "L" at SMODE2="H" during reset
when SMODE1 "H".
2
3
4
5
6
GNDL
VCOML
AINL+
AINL-
ZCAL
-
O
I
I
I
7
8
9
VD
DGND
CAL
-
-
O
10
RST
I
11
12
SMODE2
SMODE1
I
I
13
LRCK
I/O
M0038-E-04
-3-
2000/4
ASAHI KASEI
[AK5393]
14
SCLK
I/O
15
16
SDATA
FSYNC
O
I/O
17
18
MCLK
DFS
I
I
19
HPFE
I
20
21
22
23
24
25
26
27
28
TEST
BGND
AGND
VA
AINR-
AINR+
VCOMR
GNDR
VREFR
I
-
-
-
I
I
O
-
O
Serial Data Clock Pin
Data is clocked out on the falling edge of SCLK.
Slave mode:
SCLK requires more than 48fs clock.
Master mode:
SCLK outputs a 128fs(DFS="L") or 64fs(DFS="H") clock.
SCLK stays "L" during reset.
Serial Data Output Pin
MSB first, 2's complement. SDATA stays "L" during reset.
Frame Synchronization Signal Pin
Slave mode:
When "H", the data bits are clocked out on SDATA. In I
2
S mode, FSYNC is
don’t care.
Master mode:
FSYNC outputs 2fs clock. FSYNC stays "L" during reset.
Master Clock Input Pin
256fs at DFS="L", 128fs at DFS="H".
Double Speed Sampling Mode Pin
"L": Normal Speed
"H": Double Speed
High Pass Filter Enable Pin
"L": Disable
"H": Enable
Test Pin (pull-down pin)
Should be connected to GND.
Substrate Ground Pin, 0V
Analog Ground Pin, 0V
Analog Supply Pin, 5V
Rch Analog negative input Pin
Rch Analog positive input Pin
Rch Common Voltage Pin, 2.75V
Rch Reference Ground Pin, 0V
Rch Reference Voltage Pin, 3.75V
Normally connected to GNDR with a 10µF electrolytic capacitor and a 0.1µF
ceramic capacitor
Note: All digital inputs should not be left floating.
M0038-E-04
-4-
2000/4
ASAHI KASEI
[AK5393]
ABSOLUTE MAXIMUM RATINGS
(AGND,BGND,DGND=0V; Note 1)
Parameter
Power Supplies:
Analog
Digital
|BGND-DGND| (Note 2)
Input Current, Any Pin Except Supplies
Analog Input Voltage
Digital Input Voltage
Ambient Temperature (power applied)
Storage Temperature
Symbol
VA
VD
∆GND
IIN
VINA
VIND
Ta
Tstg
min
-0.3
-0.3
-
-
-0.3
-0.3
-10
-65
max
6.0
6.0
0.3
±10
VA+0.3
VD+0.3
70
150
Units
V
V
V
mA
V
V
°C
°C
Notes: 1. All voltages with respect to ground.
2. AGND, BGND and DGND must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND,BGND,DGND=0V; Note 1)
Parameter
Symbol
min
typ
5.0
3.3
max
5.25
5.25
Units
V
V
Power Supplies:
Analog
VA
4.75
(Note 3)
Digital
VD
3.0
Notes: 1. All voltages with respect to ground.
3. The power up sequence between VA and VD is not critical.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
M0038-E-04
-5-
2000/4
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