HY5RS123235FP
Revision History
Revision
No.
0.1
0.2
History
Defined target spec.
Page 11) Add Cas Latency 11
Page 14) Write Latency definitions
Page15) DI, WR_A, AL definitions
Page47) Table18 typo corrected
Page48) Table19 renewered
Page50) note 46 added
Page4) Ballout configurations correct
Appendix C) BST function description
- Non-Consectutive Read to Write timing clarifications
- Read to Precharge timing Clarifications
- Modified the pin descriptions and added command description
for BST
- Added the LP mode feature for EMRS
-Added the Lead free package part number and Package dimen-
sion page
Draft Date
Mar. 2004
JULY.2004
CL
WL
DI/WR_A/AL
Speed BIN
Several Parameters
tRPRE
A3/A8/A9/A10
Page28
page41
Page23
Page4,6,21
Page15,16
Jan.31,2005
Page3,56
Remark
0.3
0.4
Aug.2004
Sep.24,2004
0.5
Nov.8,2004
0.6
1.0
- Clarified the ODT control and Data terminator disable command
and its duration timing
- Modify the Data termination disable mode note of EMRS
- Modified the PIN description of VDDA/ VSSA(K1,12/J1,12)
- Changed the tPDIX, from 4tCK to 6tCK
- Changed the tXSRD, from 300tCk to 1000tCK
- Added the tCJC definition
- IDD spec update
- DC spec Update
Apr.30,2005
Page 15,20
Page 9
Page 4,7
Page 47
Page 48
page 48
page 46
Table 12
1.1
VDD/VDDQ change, 500Mhz Speed Bin Insert, IDD value tuning
& typo corrected
Jun. 2005
1.2
1.3
1.4
1.5
VDD/VDDQ Change at 600MHz speed bin to 1.8V from 2.0V
900MHz speed bin insert
VDD/VDDQ change for 800MHz speed bin & IDD value change
Changed Async parameter at 700/800/900MHz speed bin
(tRAS/tRC/tRFC/tRCDW/tRP/tDAL)
Nov. 2005
Feb. 2006
Mar. 2006
Apr. 2006
Rev. 1.5 / Apr. 2006
2
HY5RS123235FP
DESCRIPTION
The Hynix HY5RS123235 is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits.
The Hynix HY5RS123235 is internally configured as a eight-bank DRAM.
The Hynix HY5RS123235 uses a double data rate architecture to achieve high-speed opreration. The double date rate architecture
is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the Hynix HY5RS123235 consists of a 4n-bit wide, every two-clock-cycles data transfer at the internal DRAM
core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. Read and write accesses to the Hynix
HY5RS123235 is burst oriented; accesses start at a selected locations and continue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ of WRITE com-
mand. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed
(BA0,BA1, BA2 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command
are used to select the starting column location for the burst access. Prior to normal operation, the Hynix HY5RS123235 must be ini-
tialized.
FEATURES
•
2.2V +/-0.1V VDD/VDDQ power supply supports 900 /
800MHz
•
2.0V VDD/ VDDQ wide range min/max power supply
supports 700MHz
•
1.8V VDD/ VDDQ wide range min/max power supply
supports 500 / 600MHz
•
•
•
Single ended READ Strobe (RDQS) per byte
Single ended WRITE Strobe (WDQS) per byte
Internal, pipelined double-data-rate (DDR) architecture;
two data accesses per clock cycle
•
•
•
•
Calibrated output driver
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
RDQS edge-aligned with data for READ; with WDQS
•
•
•
•
•
•
•
•
•
•
•
•
center-aligned with data for WRITE
Eight internal banks for concurrent operation
Data mask (DM) for masking WRITE data
4n prefetch
Programmable burst lengths: 4, 8
32ms, 8K-cycle auto refresh
Auto precharge option
Auto Refresh and Self Refresh Modes
1.8V Pseudo Open Drain I/O
Concurrent Auto Precharge support
tRAS lockout support, Active Termination support
Programmable Write latency(1, 2, 3, 4, 5, 6)
Boundary Scan Feature for connectivity test(refer to JEDEC
std., not in this version of Specifications)
ORDERING INFORMATION
Part No.
HY5RS123235FP-11
HY5RS123235FP-12
HY5RS123235FP-14
HY5RS123235FP-16
HY5RS123235FP-2
Power Supply
VDD=2.2V,
VDDQ=2.2V
VDD=2.0V,
VDDQ=2.0V
VDD=1.8V,
VDDQ=1.8V
Clock Frequency
900MHz
800MHz
700MHz
600MHz
500MHz
Max Data Rate
1800Mbps/pin
1600Mbps/pin
1400Mbps/pin
1200Mbps/pin
1000Mbps/pin
POD_18
12mmx14mm
136Ball FBGA
Interface
Package
Note)
HY5RS123235FP-xx is the Lead Free Package part number
Rev. 1.5 / Apr. 2006
3
Embedded System
京公网安备 11010802033920号
EEWORLD
