TARGET SPECIFICATION
PI6C2972, PI6C2973
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Low Voltage PLL Clock Driver
Features
• Fully Integrated PLL
• Output Frequency up to 125 MHz
• Compatible with PowerPC and Pentium Microprocessors
• 3.3V V
CC
• + 100ps Typical Cycle–to–Cycle Jitter
• Available packaging: 52-pin LQFP
outputs can be realized by pulsing low one clock edge prior to
the coincident edges of the Qa and Qc outputs. The Sync output
will indicate when the coincident rising edges of the above
relationships will occur. The Power–On Reset ensures proper
programming if the frequency select pins are set at power up. If
the fselFB2 pin is held high, it may be necessary to apply a reset
after power–up to ensure synchronization between the QFB
output and the other outputs. The internal power–on reset is
designed to provide this function, but with power–up conditions
being dependent, it is difficult to guarantee. All other conditions
of the fsel pins will automatically synchronize during PLL lock
acquisition.
The PI6C2972/2973 offers a very flexible output enable/disable
scheme. Note that all of the control inputs on the PI6C2972/2973
have internal pull–up resistors.
The PI6C2972/2973 is fully 3.3V compatible and requires no
external loop filter components. All inputs accept LVCMOS/
LVTTL compatible levels while the outputs provide LVCMOS
levels with the capability to drive 50 Ohm transmission lines. For
series terminated lines each PI6C2972/2973 output can drive two
50 Ohm lines in parallel thus effectively doubling the fanout of
the device.
Description
The PI6C2972/2973 are 3.3V compatible, PLL based clock driver
devices targeted for high-performance CISC or RISC processor
based systems. With output frequencies of up to 125 MHz and
skews of 550ps the PI6C2972/2973 are ideally suited for most
synchronous systems. The devices offer twelve low skew
outputs plus a feedback and sync output for added flexibility and
ease of system implementation.
The PI6C2972/2973 features an extensive level of frequency
programmability between the 12 outputs as well as the input vs
output relationships. Using the select lines output frequency
ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 6:1 and 6:5 between
Pin Configuration - PI6C2972
fselFB0
Ext_FB
GNDO
GNDO
VCCO
VCCO
GND0
VCCI
QFB
Qb0
Qb1
Qb2
Qb3
Pin Configuration - PI6C2973
fselFB0
Ext_FB
GNDO
GNDO
VCCO
VCCO
GND0
VCCI
QFB
Qb0
Qb1
Qb2
Qb3
fselb1
fselb0
fsela1
fsela0
Qa3
VCCO
Qa2
GNDO
Qa1
VCCO
Qa0
GND0
VCO_Sel
39 38 37 36 35 34 33 32 31 30 29 28 27
26
40
41
42
43
44
45
46
47
48
49
50
51
52
1
2
3
4
5
6
7
8
25
24
23
22
21
20
19
18
17
16
15
14
9 10 11 12 13
fselFB1
QSync
GNDO
Qc0
VCCO
Qc1
fselc0
fselc1
Qc2
VCCO
Qc3
GND0
Inv_Clk
fselb1
fselb0
fsela1
fsela0
Qa3
VCCO
Qa2
GNDO
Qa1
VCCO
Qa0
GND0
VCO_Sel
39 38 37 36 35 34 33 32 31 30 29 28 27
26
40
41
42
43
44
45
46
47
48
49
50
51
52
1
2
3
4
5
6
7
8
25
24
23
22
21
20
19
18
17
16
15
14
9 10 11 12 13
fselFB1
QSync
GNDO
Qc0
VCCO
Qc1
fselc0
fselc1
Qc2
VCCO
Qc3
GND0
Inv_Clk
GND1
MR/OE
Frz_Clk
Frz_Data
fselFB2
PLL_EN
Ref_Sel
TClk_Sel
TClk0
TClk1
VCCA
xtal1
xtal2
Frz_Data
Ref_Sel
TClk_Sel
GND1
MR/OE
Frz_Clk
fselFB2
PLL_EN
TClk0
TClk1
PECL_CLK
PECL_CLK
VCCA
PSXXXX
1
07/14/00
TARGET SPECIFICATION
PI6C2972, PI6C2973
Low Voltage PLL Clock Driver
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Absolute Maximum Ratings
Symbol
V
CC
V
I
I
IN
T
STOR
Parame te r
Supply Voltage
Input Voltage
Input Current
Storage Temperature
–40
M in.
–0 . 3
–0.3
M ax.
4.6
V
DD
+0.3
±20
125
Units
V
V
mA
°C
*Absolute maximum continuous ratings are those values beyond which damage to the device may occur.
Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability.
Functional operation under absolute-maximum-rated conditions is not implied.
DC Characteristics (T
A
= 0°C to 70°C, V
CC
= 3.3V ± 5%)
Symbol
V
IH
V
IL
V
PP
V
CMR
V
OH
V
OL
I
IN
I
CC
I
CCA
C
IN
C
pd
Per Output
Note 1
I
OH
= 20mA
(2)
I
OL
= 20mA
(2)
Note 3
Conditions
Characte ris tic
Input HIGH Voltage
Input LOW Voltage
Peak- to Peak Input Voltage
PECL_CLK
Common Mode Range
PECL_CLK
Output HIGH Voltage
Output LOW Voltage
Input Current
Maximum Quiescent Supply Current
Analog V
CC
Current
Input Capacitance
Power Dissipation Capacitance
25
190
15
300
V
CC
–2.0
2.4
0.5
±120
215
mA
20
4
pF
Notes:
1. V
CMR
is the difference from the most positive side of the differential input signal. Normal operation is obtained when
the “High” input is within the V
CMR
range and the input lies within the V
PP
specification.
2. The PI6C2972/2973 outputs can drive series or parallel terminated 50 Ohm (or 50 Ohm to V
CC
/2) transmission lines on
the incident edge (see Applications Info section).
3. Inputs have pull–up/pull–down resistors which affect input current.
4. Special thermal handling may be required in some configurations.
M in.
2.0
Typ.
M ax.
3.6
Units
V
0.8
10 0 0
V
CC
–0.6
V
mV
µΑ
5
PSXXXX
07/14/00
Power technology
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