DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD4516421A, 4516821A, 4516161A for Rev. P
16M-bit Synchronous DRAM
Description
The
µ
PD4516421A, 4516821A, 4516161A are high-speed 16,777,216-bit synchronous dynamic random-access
memories, organized as 2,097,152
×
4
×
2, 1,048,576
×
8
×
2 and 524,288
×
16
×
2 (word
×
bit
×
bank), respectively.
The synchronous DRAMs achieve high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
The synchronous DRAMs are packaged in 44-pin TSOP (II) (×4,
×8)
and 50-pin TSOP (II) (×16).
Features
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Dual internal banks controlled by A11 (Bank Select)
• Programmable burst-length (1, 2, 4, 8, Full Page)
• Programmable wrap sequence (Sequential/Interleave)
• Programmable CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
•
×4, ×8, ×16
organization
• Single + 3.3
±0.3
V power supply
• LVTTL compatible
• Byte control (×16) by LDQM and UDQM
• 2,048 refresh cycles/32 ms
• Burst termination by Burst Stop command and Precharge command
The information in this document is subject to change without notice.
Document No. M12939EJ3V0DS00 (3rd edition)
Date Published April 1998 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1997
µ
PD4516421A, 4516821A, 4516161A for Rev. P
Pin Configurations
[
µ
PD4516421A]
44-pin Plastic TSOP(II) (400 mil)
µ
PD4516421AG5-9NF
V
CC
NC
V
SS
Q
DQ0
V
CC
Q
NC
V
SS
Q
DQ1
V
CC
Q
NC
NC
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
SS
NC
V
SS
Q
DQ3
V
CC
Q
NC
V
SS
Q
DQ2
V
CC
Q
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
V
SS
A0 to A11
Note
: Address inputs
DQ0 to DQ3
CLK
CKE
CS
RAS
CAS
WE
DQM
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
: Data inputs/outputs
: System clock input
: Clock enable
: Chip select
: Row address strobe
: Column address strobe
: Write enable
: DQ mask enable
: Supply voltage
: Ground
: Supply voltage for DQ
: Ground for DQ
: No connection
Note
A0 to A10 : Row address inputs
A0 to A9 : Column address inputs
A11
: Bank select
4
µ
PD4516421A, 4516821A, 4516161A for Rev. P
[
µ
PD4516821A]
44-pin Plastic TSOP(II) (400 mil)
µ
PD4516821AG5-9NF
V
CC
DQ0
V
SS
Q
DQ1
V
CC
Q
DQ2
V
SS
Q
DQ3
V
CC
Q
NC
NC
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
SS
DQ7
V
SS
Q
DQ6
V
CC
Q
DQ5
V
SS
Q
DQ4
V
CC
Q
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
V
SS
A0 to A11
Note
: Address inputs
DQ0 to DQ7
CLK
CKE
CS
RAS
CAS
WE
DQM
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
: Data inputs/outputs
: System clock input
: Clock enable
: Chip select
: Row address strobe
: Column address strobe
: Write enable
: DQ mask enable
: Supply voltage
: Ground
: Supply voltage for DQ
: Ground for DQ
: No connection
Note
A0 to A10 : Row address inputs
A0 to A8 : Column address inputs
A11
: Bank select
5
Embedded System
京公网安备 11010802033920号
EEWORLD
