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HEC4069UBT

Description
IC 4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, PDSO14, PLASTIC, SOT-108-1, SO-14, Gate
Categorylogic    logic   
File Size126KB,17 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance  
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HEC4069UBT Overview

IC 4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, PDSO14, PLASTIC, SOT-108-1, SO-14, Gate

HEC4069UBT Parametric

Parameter NameAttribute value
Source Url Status Check Date2013-06-14 00:00:00
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerNXP
Parts packaging codeSOIC
package instructionSOP,
Contacts14
Reach Compliance Codeunknown
series4000/14000/40000
JESD-30 codeR-PDSO-G14
JESD-609 codee4
length8.65 mm
Logic integrated circuit typeINVERTER
Humidity sensitivity level1
Number of functions6
Number of entries1
Number of terminals14
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)90 ns
Certification statusNot Qualified
Maximum seat height1.75 mm
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Terminal surfaceNICKEL PALLADIUM GOLD
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width3.9 mm

HEC4069UBT Preview

HEF4069UB
Hex inverter
Rev. 8 — 16 November 2011
Product data sheet
1. General description
The HEF4069UB is a general purpose hex inverter. Each inverter has a single stage.
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from
40 C
to +85
C
and
40 C
to +125
C
Complies with JEDEC standard JESD 13-B
3. Applications
Oscillator
4. Ordering information
Table 1.
Ordering information
All types operate from
40
C to +125
C.
Type number
HEF4069UBP
HEF4069UBT
HEF4069UBTT
Package
Name
DIP14
SO14
TSSOP14
Description
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads; body width 3.9 mm
plastic thin shrink small outline package; 14 leads; body width 4.4 mm
Version
SOT27-1
SOT108-1
SOT402-1
NXP Semiconductors
HEF4069UB
Hex inverter
5. Functional diagram
1A
1
2
1Y
2A
3
4
2Y
3A
5
6
3Y
4A
9
8
4Y
V
DD
5A
11
10
5Y
A
Y
6A
13
12
6Y
V
SS
001aag154
001aag152
Fig 1.
Functional diagram
Fig 2.
Schematic diagram (one inverter)
6. Pinning information
6.1 Pinning
1A
1Y
2A
2Y
3A
3Y
V
SS
1
2
3
4
5
6
7
001aag153
14 V
DD
13 6A
12 6Y
HEF4069UB
11 5A
10 5Y
9
8
4A
4Y
Fig 3.
Pin configuration
6.2 Pin description
Table 2.
Symbol
1A to 6A
1Y to 6Y
V
SS
V
DD
Pin description
Pin
1, 3, 5, 9, 11, 13
2, 4, 6, 8, 10, 12
7
14
Description
input
output
ground (0 V)
supply voltage
HEF4069UB
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 16 November 2011
2 of 17
NXP Semiconductors
HEF4069UB
Hex inverter
7. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DD
I
IK
V
I
I
OK
I
I/O
I
DD
T
stg
T
amb
P
tot
Parameter
supply voltage
input clamping current
input voltage
output clamping current
input/output current
supply current
storage temperature
ambient temperature
total power dissipation
T
amb
=
40 C
to +125
C
DIP14
SO14
TSSOP14
P
[1]
[2]
[3]
[1]
[2]
[3]
Conditions
V
I
<
0.5
V or V
I
> V
DD
+ 0.5 V
V
O
<
0.5
V or V
O
> V
DD
+ 0.5 V
Min
0.5
-
0.5
-
-
-
65
40
-
-
-
-
Max
+18
10
V
DD
+ 0.5
10
10
50
+150
+125
750
500
500
100
Unit
V
mA
V
mA
mA
mA
C
C
mW
mW
mW
mW
power dissipation
per output
For DIP14 packages: above T
amb
= 70
C,
P
tot
derates linearly with 12 mW/K.
For SO14 packages: above T
amb
= 70
C,
P
tot
derates linearly with 8 mW/K.
For TSSOP14 packages: above T
amb
= 60
C,
P
tot
derates linearly with 5.5 mW/K.
8. Recommended operating conditions
Table 4.
Symbol
V
DD
V
I
T
amb
Recommended operating conditions
Parameter
supply voltage
input voltage
ambient temperature
in free air
Conditions
Min
3
0
40
Typ
-
-
-
Max
15
V
DD
+125
Unit
V
V
C
HEF4069UB
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 16 November 2011
3 of 17
NXP Semiconductors
HEF4069UB
Hex inverter
9. Static characteristics
Table 5.
Static characteristics
V
SS
= 0 V; V
I
= V
SS
or V
DD
; unless otherwise specified.
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
I
O
< 1
A
V
DD
5V
10 V
15 V
V
IL
LOW-level
input voltage
I
O
< 1
A
5V
10 V
15 V
V
OH
HIGH-level
I
O
< 1
A
output voltage
5V
10 V
15 V
V
OL
LOW-level
I
O
< 1
A
output voltage
5V
10 V
15 V
I
OH
HIGH-level
V
O
= 2.5 V
output current V = 4.6 V
O
V
O
= 9.5 V
V
O
= 13.5 V
I
OL
LOW-level
V
O
= 0.4 V
output current V = 0.5 V
O
V
O
= 1.5 V
I
I
I
DD
input leakage
current
5V
5V
10 V
15 V
5V
10 V
15 V
15 V
T
amb
=
40 C
Min
4
8
12.5
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
0.64
1.6
4.2
-
-
-
-
-
Max
-
-
-
1
2
2.5
-
-
-
0.05
0.05
0.05
1.7
0.64
1.6
4.2
-
-
-
0.1
0.25
0.5
1.0
-
T
amb
= +25
C
Min
4
8
12.5
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
0.5
1.3
3.4
-
-
-
-
-
Max
-
-
-
1
2
2.5
-
-
-
0.05
0.05
0.05
1.4
0.5
1.3
3.4
-
-
-
0.1
0.25
0.5
1.0
7.5
T
amb
= +85
C
T
amb
= +125
C
Unit
Min
4
8
12.5
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
0.36
0.9
2.4
-
-
-
-
-
Max
-
-
-
1
2
2.5
-
-
-
0.05
0.05
0.05
1.1
0.36
0.9
2.4
-
-
-
1.0
7.5
15.0
30.0
-
Min
4
8
12.5
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
0.36
0.9
2.4
-
-
-
-
-
Max
-
-
-
1
2
2.5
-
-
-
0.05
0.05
0.05
1.1
0.9
2.4
-
-
-
1.0
7.5
15.0
30.0
-
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
A
A
A
A
pF
0.36
mA
5V
supply current all valid input
combinations; 10 V
I
O
= 0 A
15 V
input
capacitance
digital inputs
C
I
HEF4069UB
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 16 November 2011
4 of 17
NXP Semiconductors
HEF4069UB
Hex inverter
10. Dynamic characteristics
Table 6.
Dynamic characteristics
T
amb
= 25
C; for waveforms see
Figure 4;
for test circuit see
Figure 5.
Symbol Parameter
t
PHL
HIGH to LOW
propagation delay
Conditions
nA to nY;
V
DD
5V
10 V
15 V
t
PLH
LOW to HIGH
propagation delay
nA to nY
5V
10 V
15 V
t
THL
HIGH to LOW output
transition time
output nY
5V
10 V
15 V
t
TLH
LOW to HIGH output
transition time
output nY
5V
10 V
15 V
[1]
Extrapolation formula
[1]
18 ns + (0.55 ns/pF)C
L
9 ns + (0.23 ns/pF)C
L
7 ns + (0.16 ns/pF)C
L
13 ns + (0.55 ns/pF)C
L
9 ns + (0.23 ns/pF)C
L
7 ns + (0.16 ns/pF)C
L
10 ns + (1.00 ns/pF)C
L
9 ns + (0.42 ns/pF)C
L
6 ns + (0.28 ns/pF)C
L
10 ns + (1.00 ns/pF)C
L
9 ns + (0.42 ns/pF)C
L
6 ns + (0.28 ns/pF)C
L
Min
-
-
-
-
-
-
-
-
-
-
-
-
Typ
45
20
15
40
20
15
60
30
20
60
30
20
Max
90
40
25
80
40
30
120
60
40
120
60
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (C
L
in pF).
Table 7.
Dynamic power dissipation
V
SS
= 0 V; t
r
= t
f
20 ns; T
amb
= 25
C.
Symbol Parameter
P
D
dynamic power dissipation
V
DD
Typical formula
Where
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
5 V P
D
= 600
f
i
+
(f
o
C
L
)
V
DD2
(W)
10 V P
D
= 4000
f
i
+
(f
o
C
L
)
V
DD2
(W)
15 V P
D
= 22000
f
i
+
(f
o
C
L
)
V
DD2
(W) C
L
= output load capacitance in pF;
(f
o
C
L
) = sum of the outputs;
V
DD
= supply voltage in V.
HEF4069UB
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 16 November 2011
5 of 17

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