Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHX14NQ20T , PHF14NQ20T
FEATURES
•
’Trench’
technology
• Low on-state resistance
• Fast switching
SYMBOL
d
QUICK REFERENCE DATA
V
DSS
= 200 V
I
D
= 7.6 A
g
R
DS(ON)
≤
230 mΩ
s
GENERAL DESCRIPTION
N-channel enhancement mode field-effect power transistor in a plastic full pack envelope using ’trench’ technology.
The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching
applications.
The PHX14NQ20T is supplied in the SOT186A (FPAK) conventional leaded package.
PINNING
PIN
1
2
3
case
gate
drain
source
isolated
DESCRIPTION
SOT186A (FPAK)
case
SOT186 (FPAK)
case
1 2 3
1 2 3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
V
DGR
V
GS
I
D
I
DM
P
D
T
j
, T
stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
CONDITIONS
T
j
= 25 ˚C to 150˚C
T
j
= 25 ˚C to 150˚C; R
GS
= 20 kΩ
T
hs
= 25 ˚C; V
GS
= 10 V
T
hs
= 100 ˚C; V
GS
= 10 V
T
hs
= 25 ˚C
T
hs
= 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
200
200
±
20
7.6
4.8
30
30
150
UNIT
V
V
V
A
A
A
W
˚C
November 2000
1
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHX14NQ20T , PHF14NQ20T
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
E
AS
Non-repetitive avalanche
energy
Peak non-repetitive
avalanche current
CONDITIONS
Unclamped inductive load, I
AS
= 14 A;
t
p
= 38
µs;
T
j
prior to avalanche = 25˚C;
V
DD
≤
25 V; R
GS
= 50
Ω;
V
GS
= 10 V; refer
to fig 15
MIN.
-
MAX.
70
UNIT
mJ
I
AS
-
14
A
THERMAL RESISTANCES
SYMBOL PARAMETER
R
th j-hs
R
th j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
MIN.
-
SOT186A package, in free air
-
TYP. MAX. UNIT
-
55
4.17
-
K/W
K/W
ELECTRICAL CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
V
(BR)DSS
V
GS(TO)
R
DS(ON)
g
fs
I
GSS
I
DSS
Q
g(tot)
Q
gs
Q
gd
t
d on
t
r
t
d off
t
f
L
d
L
s
C
iss
C
oss
C
rss
Drain-source breakdown
voltage
Gate threshold voltage
Drain-source on-state
resistance
Forward transconductance
Gate source leakage current
Zero gate voltage drain
current
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal source inductance
Input capacitance
Output capacitance
Feedback capacitance
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA;
T
j
= -55˚C
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 150˚C
T
j
= -55˚C
V
GS
= 10 V; I
D
= 7 A
V
GS
= 10 V; I
D
= 7 A; T
j
= 150˚C
V
DS
= 25 V; I
D
= 7 A
V
GS
=
±
10 V; V
DS
= 0 V
V
DS
= 200 V; V
GS
= 0 V
T
j
= 150˚C
I
D
= 14 A; V
DD
= 160 V; V
GS
= 10 V
MIN.
200
178
2
1
-
-
-
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP. MAX. UNIT
-
-
3
-
-
150
-
12.1
10
0.05
-
38
4
13.3
25
40
83
31
4.5
7.5
1500
128
60
-
-
4
-
6
230
540
-
100
10
500
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
mΩ
mΩ
S
nA
µA
µA
nC
nC
nC
ns
ns
ns
ns
nH
nH
pF
pF
pF
V
DD
= 100 V; R
D
= 10
Ω;
V
GS
= 10 V; R
G
= 5.6
Ω
Resistive load
Measured from drain lead to centre of die
Measured from source lead to source
bond pad
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
November 2000
2
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHX14NQ20T , PHF14NQ20T
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
I
S
I
SM
V
SD
t
rr
Q
rr
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
MIN.
-
-
I
F
= 14 A; V
GS
= 0 V
I
F
= 14 A; -dI
F
/dt = 100 A/µs;
V
GS
= 0 V; V
R
= 30 V
-
-
-
TYP. MAX. UNIT
-
-
1.0
135
690
14
56
1.5
-
-
A
A
V
ns
nC
ISOLATION LIMITING VALUE & CHARACTERISTIC
T
hs
= 25 ˚C unless otherwise specified
SYMBOL
V
isol
PARAMETER
R.M.S. isolation voltage from all
three terminals to external
heatsink
Repetitive peak voltage from all
three terminals to external
heatsink
Capacitance from pin 2 to
external heatsink
CONDITIONS
SOT186A package; f = 50-60 Hz;
sinusoidal waveform; R.H.
≤
65%;
clean and dustfree
SOT186 package; R.H.
≤
65%;
clean and dustfree
f = 1 MHz
MIN.
-
TYP.
MAX.
2500
UNIT
V
V
isol
-
1500
V
C
isol
-
10
-
pF
November 2000
3
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHX14NQ20T , PHF14NQ20T
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
with heatsink compound
10
Transient thermal impedance, Zth j-a (K/W)
D = 0.5
1
0.2
0.1
0.05
0.1
0.02
single pulse
0
20
40
60
80
Ths / C
100
120
140
0.01
1E-06
1E-05
1E-04
1E-03 1E-02 1E-01
Pulse width, tp (s)
1E+00
1E+01
Fig.1. Normalised power dissipation.
PD% = 100⋅P
D
/P
D 25 ˚C
= f(T
mb
)
Normalised Current Derating
with heatsink compound
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
Drain Current, ID (A)
10V
25
20
15
10
5V
5
VGS=4.5
0
0
1
2
3
4
5
6
7
8
9
10
5.5
15V
6.5V
6V
120
110
100
90
80
70
60
50
40
30
20
10
0
ID%
30
0
20
40
60
80
Ths / C
100
120
140
Drain-Source Voltage, VDS (V)
Fig.2. Normalised continuous drain current.
ID% = 100⋅I
D
/I
D 25 ˚C
= f(T
mb
); conditions: V
GS
≥
10 V
Peak Pulsed Drain Current, IDM (A)
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
GS
Drain-Source On Resistance, RDS(on) (Ohms)
0.8
0.7
4.5V
5V
5.5V
0.5
1000
100
RDS(on) = VDS/ ID
tp = 10 us
0.6
10
100us
1 ms
1
D.C.
10 ms
100 ms
0.1
1
10
100
Drain-Source Voltage, VDS (V)
1000
0.4
0.3
0.2
0.1
0
0
10
Drain Current, ID (A)
6V
6.5V
10V
VGS =20 V
20
Fig.3. Safe operating area. T
mb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
GS
November 2000
4
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHX14NQ20T , PHF14NQ20T
Drain current, ID (A)
28
24
20
16
12
8
4
0
0
2
4
6
Gate-source voltage, VGS (V)
8
10
150 C
Tj = 25 C
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
VGS(TO) / V
max
typ
min
0
-100
-50
0
Tj / C
50
100
150
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
Transconductance, gfs (S)
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Sub-Threshold Conduction
20
1E-01
15
1E-02
2%
typ
98%
10
1E-03
1E-04
5
1E-05
0
0
4
8
12
16
ID / (A)
20
24
28
1E-06
0
1
2
3
4
5
Fig.8. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
Capacitances, Ciss, Coss, Crss (pF)
2.5
a
Rds(on) normalised to 25 deg C
10000
Ciss
2
1000
Coss
100
1.5
1
Crss
0.5
-70
-20
30
80
Ths / deg C
130
10
0
10
20
30
40
Drain-Source Voltage, VDS (V)
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 7 A; V
GS
= 10 V
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
November 2000
5
Rev 1.100
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