PRELIMINARY
MT28F004B1
512K x 8 FLASH MEMORY
FLASH MEMORY
FEATURES
• Seven erase blocks:
16KB boot block (protected)
Two 8KB parameter blocks
Four main memory blocks
• Deep Power-Down Mode: 8µA at 5V V
CC
; 8µA at
3.3V V
CC
MAX
• SmartVoltage* Technology (SVT):
3.3V
±0.3V
or 5V
±10%
V
CC
5V
±10%
or 12V
±5%
V
PP
• Address access times:
60ns, 80ns, 100ns at 5V V
CC
90ns, 110ns, 150ns at 3.3V V
CC
• Industry-standard pinouts
• Inputs and outputs are fully TTL-compatible
• Automated write and erase algorithm
512K x 8
S
MART
V
OLTAGE
, BOOT BLOCK
PIN ASSIGNMENT (Top View)
40-Pin TSOP Type I
(FB-1)
OPTIONS
• Timing (5V V
CC
/3.3V V
CC
)
60ns/90ns access
80ns/110ns access
100ns/150ns access
• Boot Block Starting Address
Top (7FFFFH)
Bottom (00000H)
MARKING
- 6
- 8
-10
T
B
VG
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RP#
V
PP
WP#
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
Vss
NC
NC
A10
DQ7
DQ6
DQ5
DQ4
Vcc
Vcc
NC
DQ3
DQ2
DQ1
DQ0
OE#
Vss
CE#
A0
• Packages
Plastic 40L TSOP Type 1 (10 x 20mm)
• Part Number Example: MT28F004B1VG-8 T
GENERAL DESCRIPTION
The MT28F004B1 is a nonvolatile, electrically block-
erasable (Flash), programmable read-only memory con-
taining 4,194,304 bits organized as 524,288 words by 8 bits.
SmartVoltage Technology (SVT) provides industry-
standard, multi- or single-voltage, dual-supply operation.
Writing or erasing the device is done with either a 5V or 12V
V
PP
voltage, while all operations are performed with a 3.3V
or 5V V
CC
. It is fabricated with Micron’s advanced CMOS
floating-gate process.
The MT28F004B1 is organized into seven separately
erasable blocks. To ensure that critical firmware is protected
MT28F004B1
F17.pm5 – Rev. 9/96
from accidental erasure or overwrite, the MT28F004B1
features a hardware-protected boot block. Writing or erasing
the boot block requires either applying a super-voltage to
the RP# pin or driving WP# HIGH, in addition to executing
the normal write or erase sequences. This block may be used
to store code implemented in low-level system recovery.
The remaining blocks vary in density and are written and
erased with no additional security measures.
The byte address is issued to read the memory array with
CE# and OE# LOW and WE# HIGH. Valid data is output
until the next address is issued or CE# or OE# go HIGH.
1
Micron Quantum Devices, Inc., reserves the right to change products or specifications without notice.
©1996,
Micron Quantum Devices, Inc.
*All registered and unregistered trademarks are the sole property of their respective companies.
PRELIMINARY
MT28F004B1
512K x 8 FLASH MEMORY
PIN DESCRIPTIONS
TSOP PIN
NUMBERS
9
SYMBOL
WE#
TYPE
Input
DESCRIPTION
Write Enable: Determines if a given cycle is a write cycle. If WE# = LOW,
the cycle is either a WRITE to the Command Execution Logic (CEL) or to
the memory array.
Chip Enable: Activates the device when LOW. When CE# is HIGH, the
device is disabled and goes into standby power mode.
Write Protect: Unlocks the boot block when HIGH if V
PP
=
V
PPH
1
(5V) or
V
PPH
2
(12V) and RP# = V
IH
during a write or erase. Does not affect write
or erase operation on other blocks.
Reset Power-Down: Clears the status register, sets the Internal State
Machine (ISM) to the array read mode, and places the device in deep
power-down mode when LOW. All inputs, including CE#, are “don’t care”
and all outputs are High-Z. Also used to unlock boot block when brought
to V
HH
(boot block unlock voltage; 12V). Overrides condition of WP#
when at V
HH
. Must be held at V
IH
during all other modes of operation.
Output Enable: Enables data output buffers when LOW. When OE# is
HIGH, the output buffers are disabled.
Address Inputs: Selects a unique byte out of the 524,288 available.
22
12
CE#
WP#
Input
Input
10
RP#
Input
24
21, 20, 19, 18,
17, 16, 15, 14,
8, 7, 36, 6, 5, 4,
3, 2, 1, 40, 13
25, 26, 27, 28,
32, 33, 34, 35
29, 37, 38
11
OE#
A0-A18
Input
Input
DQ0-DQ7
Input/
Output
-
Supply
Data I/O: Data output pins during any read operation, or data input pins
during a WRITE. Used to input commands to the CEL for a command
input.
No Connect: These pins may be driven or left unconnected.
Write/Erase Supply Voltage: From a WRITE or ERASE CONFIRM until
completion of the write or erase, V
PP
must be at V
PPH
1
(5V) or V
PPH
2
(12V). V
PP
= “don’t care” during all other operations.
Power Supply: +5V
±10%
or +3.3V
±0.3V.
Ground.
NC
V
PP
30, 31
23, 39
V
CC
V
SS
Supply
Supply
MT28F004B1
F17.pm5 – Rev. 9/96
3
Micron Quantum Devices, Inc., reserves the right to change products or specifications without notice.
©1996,
Micron Quantum Devices, Inc.
PRELIMINARY
MT28F004B1
512K x 8 FLASH MEMORY
FUNCTIONAL DESCRIPTION
The MT28F004B1 Flash memory incorporates a number
of features to make it ideally suited for system firmware.
The memory array is segmented into individual erase
blocks. Each block may be erased without affecting data
stored in other blocks. These memory blocks are read,
written and erased by issuing commands to the Command
Execution Logic (CEL). The CEL controls the operation of
the Internal State Machine (ISM), which completely con-
trols all write, block erase and verify operations. The ISM
protects each memory location from over-erasure and
optimizes each memory location for maximum data reten-
tion. In addition, the ISM greatly simplifies the control
necessary for writing the device in-system or in an external
programmer.
The Functional Description provides detailed informa-
tion on the operation of the MT28F004B1 and is organized
into these sections:
•
•
•
•
•
•
•
•
•
•
•
Overview
Memory Architecture
Output (Read) Operations
Input Operations
Command Set
ISM Status Register
Command Execution
Error Handling
Write/Erase Cycle Endurance
Power Usage
Power-up
remaining blocks require only the V
PP
voltage be present on
the V
PP
pin before writing or erasing.
HARDWARE-PROTECTED BOOT BLOCK
This block of the memory array can be erased or written
only when the RP# pin is taken to V
HH
or when the WP# pin
is brought HIGH. This provides additional security for the
core firmware during in-system firmware updates, should
an unintentional power fluctuation or system reset occur.
The MT28F004B1 is available in two versions: the
MT28F004B1T addresses the boot block starting from
7FFFFH, and the MT28F004B1B addresses the boot block
starting from 00000H.
INTERNAL STATE MACHINE (ISM)
Block erase and write timing are simplified by using an
ISM to control all erase and write algorithms in the memory
array. The ISM ensures protection against over-erasure and
optimizes write margin to each cell.
During write operations, the ISM automatically incre-
ments and monitors write attempts, verifies write margin
on each memory cell, and updates the ISM status register.
When block erase is performed, the ISM automatically
overwrites the entire addressed block (eliminates over-
erasure), increments and monitors erase attempts, and sets
bits in the ISM status register.
ISM STATUS REGISTER
The ISM status register allows an external processor to
monitor the status of the ISM during write and erase opera-
tions. Two bits of the 8-bit status register are set and cleared
entirely by the ISM. These bits indicate whether the ISM is
busy with an erase or write task and when an erase has been
suspended. Additional error information is set in three
other bits: valid V
PP
voltage, write error and erase error.
COMMAND EXECUTION LOGIC (CEL)
The CEL receives and interprets commands to the device.
These commands control the operation of the ISM and the
read path (i.e., memory array, ID register, or status register).
Commands may be issued to the CEL while the ISM is
active. However, there are restrictions on what commands
are allowed in this condition. See the Command Execution
section for more detail.
DEEP POWER-DOWN MODE
To allow for maximum power conservation, the
MT28F004B1 features a very low current, deep power-
down mode. To enter this mode, the RP# pin is taken to V
SS
±0.2V.
In this mode, the current draw is a maximum of 8µA
at 5V V
CC
and 2µA at 3.3V V
CC
. Entering deep power-down
OVERVIEW
S
MART
V
OLTAGE
TECHNOLOGY (SVT)
SmartVoltage Technology allows maximum flexibility
for in-system READ, WRITE and ERASE operations. For
5V-only systems, WRITE and ERASE operations may be
executed with a V
PP
voltage of 5V. If 12V is available in a
system, the highest ERASE and WRITE performance can be
achieved with a V
PP
voltage of 12V. For any operation, V
CC
may be at 3.3V or 5V.
SEVEN INDEPENDENTLY ERASABLE MEMORY
BLOCKS
The MT28F004B1 is organized into seven independently
erasable memory blocks that allow portions of the memory
to be erased without affecting the rest of the memory
data. A special boot block is hardware-protected against
inadvertent erasure or writes by requiring either a super-
voltage on the RP# pin or driving the WP# (write protect)
pin HIGH. One of these two conditions must exist along
with the V
PP
voltage (5V or 12V) on the V
PP
pin before a
WRITE or ERASE will be performed on the boot block. The
MT28F004B1
F17.pm5 – Rev. 9/96
5
Micron Quantum Devices, Inc., reserves the right to change products or specifications without notice.
©1996,
Micron Quantum Devices, Inc.
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