STM8AH619ATBXXXU datasheet, PDF - EEWORLD Datasheet

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STM8AH619ATBXXXU: Description8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP80, 14 X 14 MM, ROHS COMPLIANT, LQFP-80; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，118 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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STM8AH619ATBXXXU Overview

8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP80, 14 X 14 MM, ROHS COMPLIANT, LQFP-80

STM8AH619ATBXXXU Parametric

Parameter Name	Attribute value
Maker	STMicroelectronics
Parts packaging code	QFP
package instruction	LQFP,
Contacts	80
Reach Compliance Code	unknown
Has ADC	YES
Address bus width
bit size	8
maximum clock frequency	24 MHz
DAC channel	NO
DMA channel	NO
External data bus width
JESD-30 code	S-PQFP-G80
length	14 mm
Number of I/O lines	70
Number of terminals	80
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE
Certification status	Not Qualified
ROM programmability	FLASH
Maximum seat height	1.6 mm
speed	24 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
width	14 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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STM8AF51xx STM8AF6169 STM8AF617x

STM8AF618x STM8AF619x STM8AF61Ax

Automotive 8-bit MCU, with up to 128 Kbytes Flash, data EEPROM,

10-bit ADC, timers, LIN, CAN, USART, SPI, I

2

C, 3 to 5.5 V

Features

■

Core

– Max f

CPU

: 24 MHz

– Advanced STM8A core with Harvard

architecture and 3-stage pipeline

– Average 1.6 cycles/instruction resulting in

10 MIPS at 16 MHz f

CPU

for industry

standard benchmark

Memories

– Program memory: 32 to 128 Kbytes Flash

program; data retention 20 years at 55 °C

– Data memory: up to 2 Kbytes true data

EEPROM; endurance 300 kcycles

– RAM: 2 Kbytes to 6 Kbytes

Clock management

– Low-power crystal resonator oscillator with

external clock input

– Internal, user-trimmable 16 MHz RC and

low-power 128 kHz RC oscillators

– Clock security system with clock monitor

Reset and supply management

– Multiple low-power modes (wait, slow, auto-

wakeup, halt) with user definable clock

gating

– Low consumption power-on and

power-down reset

Interrupt management

– Nested interrupt controller with 32 interrupt

vectors

– Up to 37 external interrupts on 5 vectors

Timers

– 2 auto-reload 16-bit PWM timers with up to

3 CAPCOM channels each (IC, OC or

PWM)

– Multipurpose timer: 16-bit, 4 CAPCOM

channels, 3 complementary outputs, dead-

time insertion and flexible synchronization

– 8-bit AR system timer with 8-bit prescaler

– Auto-wakeup timer

– Window and standard watchdog timers

Operating temperature up to 145 °C

■

LQFP48 7x7

LQFP80 14x14

LQFP32 7x7

LQFP64 10x10

■

■

Communication interfaces

– High speed 1 Mbit/s active CAN 2.0B

interface

– USART with clock output for synchronous

operation - LIN master mode

– LINUART LIN 2.1 compliant, master/slave

modes with automatic resynchronization

– SPI interface up to 10 Mbit/s or f

CPU

/2

– I

2

C interface up to 400 Kbit/s

Analog to digital converter (ADC)

– 10-bit resolution, 2 LSB TUE, 1 LSB

linearity and up to 16 multiplexed channels

I/Os

– Up to 72 user pins including 10 high sink

I/Os

– Highly robust I/O design, immune against

current injection

Device summary

(1)

■

■

■

■

Table 1.

Part numbers: STM8AF51xx (CAN)

STM8AF51AA, STM8AF51A9, STM8AF51A8,

STM8AF519A, STM8AF5199, STM8AF5198,

STM8AF518A, STM8AF5189, STM8AF5188,

STM8AF5179, STM8AF5178, STM8AF5169, STM8AF5168

Part numbers: STM8AF61xx

STM8AF61AA, STM8AF61A9, STM8AF61A8, STM8AF619A,

STM8AF6199, STM8AF6198, STM8AF618A, STM8AF6189,

STM8AF6188,

STM8AF6186, STM8AF6179, STM8AF6178,

STM8AF6176, STM8AF6169

■

■

1. This datasheet applies to product versions with and

without data EEPROM. In the order code, the letter ‘F’

applies to devices featuring Flash and data EEPROM.

‘F’ is replaced by ‘H’ for devices with Flash only, and

by ‘P’ for devices with FASTROM (see

Table 2,

Table 3,

and

Figure 50).

April 2010

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1

Contents

STM8AF51xx, STM8AF61xx

Contents

1

2

3

4

5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1

STM8A central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1.1

5.1.2

5.1.3

Architecture and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.2

Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 15

5.2.1

5.2.2

SWIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.3

5.4

Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Flash program and data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.4.1

5.4.2

5.4.3

5.4.4

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Write protection (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Protection of user boot code (UBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Read-out protection (ROP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.5

Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.5.1

5.5.2

5.5.3

5.5.4

5.5.5

5.5.6

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Internal 16 MHz RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Internal 128 kHz RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Internal high-speed crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

External clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.6

5.7

Low-power operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.7.1

5.7.2

5.7.3

Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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5.7.4

5.7.5

Contents

Multipurpose and PWM timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

System timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.8

5.9

Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.9.1

5.9.2

5.9.3

5.9.4

5.9.5

Universal synchronous/asynchronous receiver transmitter (USART) . . 21

Universal asynchronous receiver/transmitter with LIN support

(LINUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Inter integrated circuit (I

2

C) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Controller area network interface (beCAN) . . . . . . . . . . . . . . . . . . . . . . 25

5.10

Input/output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6

Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1

6.2

Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7

Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.1

7.2

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

7.2.6

7.2.7

7.2.8

I/O register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Non volatile memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Clock and clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.3

Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

8

9

10

Interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

10.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

10.1.1

10.1.2

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

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Contents

10.1.3

10.1.4

10.1.5

STM8AF51xx, STM8AF61xx

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.2

10.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

10.3.1

10.3.2

10.3.3

10.3.4

10.3.5

10.3.6

10.3.7

10.3.8

10.3.9

VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 73

Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 75

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

TIM 1, 2, 3, and 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 85

SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

10.3.10 I

2

C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

10.3.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

10.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

10.4

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

10.4.1

10.4.2

Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 96

11

Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

11.1

11.2

ECOPACK

®

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

12

13

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.1

STM8A core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.1.1

13.1.2

13.1.3

13.1.4

Wait for event instruction (WFE) not available . . . . . . . . . . . . . . . . . . . 103

JRIL and JRIH instructions not available . . . . . . . . . . . . . . . . . . . . . . . 103

CPU not returning to Halt mode when the AL bit is set . . . . . . . . . . . . 103

Main program not resuming after ISR has reset the AL bit . . . . . . . . . 103

13.2

I

2

C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

13.2.1

13.2.2

Misplaced NACK bit when receiving 2 bytes in master mode . . . . . . . 104

Data register corrupted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

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13.2.3

13.2.4

Contents

Delay in STOP bit programming leading to reception of supplementary

byte 105

START condition badly generated after misplaced STOP . . . . . . . . . . 105

13.3

13.4

USART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Parity error flag (PE) not correctly set when overrun condition occurs . . . . . . . . 105

LINUART interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

13.4.1

13.4.2

13.4.3

13.4.4

13.4.5

Framing error with data byte 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Framing error when receiving an identifier (ID) . . . . . . . . . . . . . . . . . . 106

Parity error when receiving an identifier (ID) . . . . . . . . . . . . . . . . . . . . 106

OR flag not correctly set in LIN master mode . . . . . . . . . . . . . . . . . . . 106

LIN header error when automatic resynchronization is enabled . . . . . 107

13.5

13.6

13.7

Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

13.5.1

HSI RC oscillator cannot be switched off in run mode . . . . . . . . . . . . . 107

SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

13.6.1

Last bit too short if SPI is disabled during communication . . . . . . . . . 107

beCAN interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

13.7.1

13.7.2

13.7.3

13.7.4

beCAN transmission error when sleep mode is entered during

transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

beCAN woken up from sleep mode with automatic wakeup interrupt . 108

beCAN time triggered communication mode not supported . . . . . . . . 108

be CAN read error in slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

14

STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

14.1

14.2

Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . 110

14.1.1

STice key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

14.2.1

14.2.2

STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

14.3

Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

15

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

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