1997-4/1
MITSUBISHI LSIs
M5M51008BP,FP,VP,RV,KV,KR -55L,-70L,-10L,
-55LL,-70LL,-10LL-I
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
DESCRIPTION
The M5M51008BP,FP,VP,RV,KV,KR are a 1048576-bit CMOS
static RAM organized as 131072 word by 8-bit which are
fabricated using high-performance triple polysilicon CMOS
technology. The use of resistive load NMOS cells and CMOS
periphery result in a high density and low power static RAM.
They are low standby current and low operation current and ideal
for the battery back-up application.
The M5M51008BVP,RV,KV,KR are packaged in a 32-pin thin
small outline package which is a high reliability and high density
surface mount device(SMD).Two types of devices are available.
VP,KV(normal lead bend type package),RV,KR(reverse lead bend
type package). Using both types of devices, it becomes very easy
to design a printed circuit board.
PIN CONFIGURATION (TOP VIEW)
NC
1
A
16 2
A
14 3
A
12 4
5
A
7
6
A
6
7
A
5
8
A
4
9
A
3
A
2 10
A
1 11
A
0 12
DQ
1 13
DQ
2 14
DQ
3 15
GND
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
ADDRESS
INPUTS
V
CC
ADDRESS
A
15
INPUT
S
2 CHIP SELECT
INPUT
W
WRITE CONTROL
INPUT
A
13
A
8
ADDRESS
INPUTS
A
9
A
11
OE
OUTPUT ENABLE
INPUT
A
10
ADDRESS
INPUT
S
1 CHIP SELECT
INPUT
DQ
8
DQ
7
DQ
6
DATA
INPUTS/
M5M51008BP,FP-I
FEATURES
Power supply current
Type name
M5M51008BP,FP,VP,RV,KV,KR-55L
M5M51008BP,FP,VP,RV,KV,KR-70L
M5M51008BP,FP,VP,RV,KV,KR-10L
M5M51008BP,FP,VP,RV,KV,KR-55LL
M5M51008BP,FP,VP,RV,KV,KR-70LL
M5M51008BP,FP,VP,RV,KV,KR-10LL
Access time
(max)
Active
(1MHz)
(max)
stand-by
(max)
DATA
INPUTS/
OUTPUTS
55ns
70ns
100ns
55ns
70ns
100ns
DQ
5
OUTPUTS
DQ
4
15mA
200µA
(Vcc=5.5V)
Outline 32P4(P), 32P2M-A(FP)
A
11
A
9
A
8
A
13
W
S
2
A
15
V
CC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
40µA
15mA
(Vcc=5.5V)
0.3µA
(Vcc=3.0V,typ)
OE
A
10
S
1
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
GND
DQ
3
DQ
2
DQ
1
A
0
A
1
A
2
A
3
Single +5V power supply
Low stand-by current 0.3µA (typ.)
Directly TTL compatible : All inputs and outputs
Easy memory expansion and power down by S
1
,S
2
Data hold on +2V power supply
Three-state outputs : OR - tie capability
OE prevents data contention in the I/O bus
Common data I/O
Package
M5M51008BP
············
32pin 600mil DIP
M5M51008BFP
············
32pin 525mil SOP
M5M51008BVP,RV
············
32pin 8 X 20 mm
2
TSOP
M5M51008BKV,KR
············
32pin 8 X 13.4 mm
2
TSOP
M5M51008BVP,KV-I
25
24
23
22
21
20
19
18
17
APPLICATION
Small capacity memory units
A
4
A
5
A
6
A
7
A
12
A
14
A
16
NC
V
CC
A
15
S
2
W
A
13
A
8
A
9
A
11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Outline 32P3H-E(VP), 32P3K-B(KV)
17
18
19
20
21
22
23
M5M51008BRV,KR-I
24
25
26
27
28
29
30
31
32
A
3
A
2
A
1
A
0
DQ
1
DQ
2
DQ
3
GND
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
S
1
A
10
OE
Outline 32P3H-F(RV), 32P3K-C(KR)
NC : NO CONNECTION
1
MITSUBISHI
ELECTRIC
1997-4/1
MITSUBISHI LSIs
M5M51008BP,FP,VP,RV,KV,KR -55L,-70L,-10L,
-55LL,-70LL,-10LL-I
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
FUNCTION
The operation mode of the M5M51008B series are determined by
a combination of the device control inputs S
1
,S
2
,W and OE.
Each mode is summarized in the function table.
A write cycle is executed whenever the low level W overlaps with
the low level S
1
and the high level S
2
. The address must be set up
before the write cycle and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W,S
1
or
S
2
,whichever occurs first,requiring the set-up and hold time
relative to these edge to be maintained. The output enable input
OE directly controls the output stage. Setting the OE at a high
level, the output stage is in a high-impedance state, and the data
bus contention problem in the write cycle is eliminated.
A read cycle is executed by setting W at a high level and OE at a
low level while S
1
and S
2
are in an active state(S
1
=L,S
2
=H).
When setting S
1
at a high level or S
2
at a low level, the chip are
in a non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high- impedance
state, allowing OR-tie with other chips and memory expansion by
S
1
and S
2
. The power supply current is reduced as low as the
stand-by current which is specified as I
CC3
or I
CC4
, and the
memory data can be held at +2V power supply, enabling battery
back-up operation during power failure or power-down operation in
the non-selected mode.
FUNCTION TABLE
S
1
X
H
L
L
L
S
2
L
X
H
H
H
W
X
X
L
H
H
Mode
DQ
OE
X Non selection High-impedance
X Non selection High-impedance
Din
X
Write
Dout
L
Read
High-impedance
H
I
CC
Stand-by
Stand-by
Active
Active
Active
BLOCK DIAGRAM
*
A4
A5
A6
A7
8
7
6
5
16
15
*
21
13 DQ1
14 DQ2
15 DQ3
17 DQ4
18 DQ5
19 DQ6
20 DQ7
21 DQ8
DATA
INPUTS/
OUTPUTS
22
ADDRESS INPUT
BUFFER
13
12
11
10
7
4
3
OUTPUT
BUFFER
14
ROW
DECODER
A12 4
A14 3
A16 2
A15 31
A13 28
A8 27
131072 WORDS
X 8 BITS
(1024 ROWS
X128 COLUMNS
X 8BLOCKS)
SENSE AMP.
23
25
26
27
28
29
ADDRESS INPUT
BUFFER
A2 10
A3
9
18
17
31
A10 23
COLUMN
DECODER
A0 12
20
CLOCK
GENERATOR
DATA INPUT
BUFFER
ADDRESS
INPUTS
5
ADDRESS INPUT
BUFFER
WRITE
29 W CONTROL
INPUT
22 S1
30 S2
CHIP
SELECT
INPUTS
BLOCK
DECODER
A1 11
A11 25
A9 26
19
1
2
30
6
32
8
24
OUTPUT
24 OE ENABLE
INPUT
32 V
CC
GND
16 (0V)
* Pin numbers inside dotted line show those of TSOP
2
MITSUBISHI
ELECTRIC
1997-4/1
MITSUBISHI LSIs
M5M51008BP,FP,VP,RV,KV,KR -55L,-70L,-10L,
-55LL,-70LL,-10LL-I
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
V
I
V
O
P
d
T
opr
T
stg
Parameter
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
Conditions
With respect to GND
Ta=25°C
Ratings
– 0.3*~7
– 0.3*~Vcc + 0.3
0~Vcc
700
– 40~85
– 65~150
Unit
V
V
V
mW
°C
°C
* –3.0V in case of AC ( Pulse width
≤
30ns )
DC ELECTRICAL CHARACTERISTICS
(Ta = –40~85°C, Vcc=5V±10%, unless otherwise noted)
Symbol
V
IH
V
IL
V
OH1
V
OH2
V
OL
I
I
I
O
Parameter
High-level input voltage
Low-level input voltage
High-level output voltage 1
High-level output voltage 2
Low-level output voltage
Input current
Output current in off-state
Active supply current
(AC, MOS level)
I
OH
=
–
0.5mA
I
OH
=
–
0.05mA
I
OL
=2mA
V
I
=0~Vcc
S
1
=V
IH
or S
2
=V
IL
or OE=V
IH
V
I/O
=0~V
CC
S
1
≤0.2V,S
2
≥Vcc–0.2V,
other inputs≤0.2V or
≥Vcc–0.2V
Output-open(duty 100%)
S
1
=V
IL
,S
2
=V
IH
,
other inputs=V
IH
or V
IL
Output-open(duty 100%)
1) S
2
≤
0.2V
2) S
1
≥
V
CC
–0.2V,
S
2
≥
V
CC
–0.2V
other inputs=0~V
CC
S
1
=V
IH
or S
2
=V
IL
,
other inputs=0~V
CC
Min
cycle
1MHz
Min
cycle
1MHz
-L
-LL
35
(40)**
4
38
(43)**
5
Test conditions
Min
2.2
–
0.3*
Limits
Typ
Max
Vcc
+0.3V
Unit
V
V
V
V
0.4
±1
±1
70
(80)**
15
70
(85)**
15
100
µA
20
3
mA
mA
V
µA
µA
0.8
2.4
Vcc
-0.5V
I
CC1
mA
I
CC2
Active supply current
(AC, TTL level)
I
CC3
Stand-by current
I
CC4
Stand-by current
* –3.0V in case of AC ( Pulse width
≤
30ns )
** inside ( ) is a value of -55L,-55LL
CAPACITANCE
(Ta = –40~85°C, Vcc=5V±10%, unless otherwise noted)
Symbol
C
I
C
O
Parameter
Input capacitance
Output capacitance
Test conditions
V
I
=GND, V
I
=25mVrms, f=1MHz
V
O
=GND,V
O
=25mVrms, f=1MHz
Min
Limits
Typ
Max
6
8
Unit
pF
pF
Note 1: Direction for current flowing into an IC is positive (no mark).
2: Typical value is Vcc = 5V, Ta = 25°C
3
MITSUBISHI
ELECTRIC
1997-4/1
MITSUBISHI LSIs
M5M51008BP,FP,VP,RV,KV,KR -55L,-70L,-10L,
-55LL,-70LL,-10LL-I
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS
(Ta = –40~85°C, Vcc=5V±10%, unless otherwise noted)
(1) MEASUREMENT CONDITIONS
Input pulse level ·············· V
IH
=2.4V,V
IL
=0.6V (-70L,-10L,-70LL,-10LL)
V
IH
=3.0V,V
IL
=0.0V (-55L,-55LL)
Input rise and fall time ····· 5ns
Reference level ················ V
OH
=V
OL
=1.5V
Output loads ····················· Fig.1,C
L
=100pF (-10L,-10LL,)
C
L
=30pF (-55L,-70L,-55LL,-70LL)
C
L
=5pF (for t
en
,t
dis
)
Transition is measured ± 500mV from steady
state voltage. (for t
en
,t
dis
)
V
CC
1.8kΩ
DQ
990Ω
C
L
( Including scope
and JIG )
Fig.1 Output load
(2) READ CYCLE
Limits
Symbol
t
CR
t
a(A)
t
a(S1)
t
a(S2)
t
a(OE)
t
dis(S1)
t
dis(S2)
t
dis(OE)
t
en(S1)
t
en(S2)
t
en(OE)
t
V(A)
Parameter
Read cycle time
Address access time
Chip select 1 access time
Chip select 2 access time
Output enable access time
Output disable time after S
1
high
Output disable time after S
2
low
Output disable time after OE high
Output enable time after S
1
low
Output enable time after S
2
high
Output enable time after OE low
Data valid time after address
-55L,LL
Min
Max
55
55
55
55
30
20
20
20
5
5
5
5
10
10
5
10
-70L,LL
Min
Max
70
70
70
70
35
25
25
25
10
10
5
10
-10L,LL
Min
Max
100
100
100
100
50
35
35
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3) WRITE CYCLE
Symbol
t
CW
t
w(W)
t
su(A)
t
su(A-WH)
t
su(S1)
t
su(S2)
t
su(D)
t
h(D)
t
rec(W)
t
dis(W)
t
dis(OE)
t
en(W)
t
en(OE)
Parameter
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to W
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recovery time
Output disable time from W low
Output disable time from OE high
Output enable time from W high
Output enable time from OE low
-55L,LL
Min
Max
55
45
0
50
50
50
25
0
0
20
20
5
5
5
5
Limits
-70L,LL
Min
Max
70
55
0
65
65
65
30
0
0
25
25
5
5
-10L,LL
Min
Max
100
75
0
85
85
85
40
0
0
35
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
MITSUBISHI
ELECTRIC
1997-4/1
MITSUBISHI LSIs
M5M51008BP,FP,VP,RV,KV,KR -55L,-70L,-10L,
-55LL,-70LL,-10LL-I
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
(4) TIMING DIAGRAMS
Read cycle
t
CR
A
0~16
t
a(A)
t
v (A)
t
a (S1)
S
1
(Note 3)
(Note 3)
t
dis (S1)
S
2
(Note 3)
t
a (S2)
t
a (OE)
t
en (OE)
t
dis (S2)
(Note 3)
OE
(Note 3)
t
dis (OE)
t
en (S1)
t
en (S2)
(Note 3)
DQ
1~8
W = "H" level
DATA VALID
Write cycle (W control mode)
t
CW
A
0~16
t
su (S1)
S
1
(Note 3)
(Note 3)
S
2
(Note 3)
t
su (S2)
(Note 3)
t
su (A-WH)
OE
t
su (A)
W
t
w (W)
t
rec (W)
t
dis (W)
t
dis (OE)
DQ
1~8
t
en (W)
DATA IN
STABLE
t
su (D)
t
h (D)
t
en(OE)
5
MITSUBISHI
ELECTRIC
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