MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
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MCM6323A
64K x 16 Bit 3.3 V Asynchronous
Fast Static RAM
The MCM6323A is a 1,048,576 bit static random access memory organized
as 65,536 words of 16 bits. Static design eliminates the need for external clocks
or timing strobes; CMOS circuitry reduces power consumption and provides for
greater reliability.
The MCM6323A is equipped with chip enable (E), write enable (W), and output
enable (G) pins, allowing for greater system flexibility and eliminating bus con-
tention problems. Separate byte enable controls (LB and UB) allow individual
bytes to be written and read. LB controls the 8 DQa bits, while UB controls the
8 DQb bits.
The MCM6323A is available in a 400 mil small–outline J–leaded (SOJ) pack-
age and a 44–lead TSOP Type II package in copper leadframe for optimum
printed circuit board (PCB) reliability.
•
•
•
•
•
•
•
•
Single 3.3 V
±
0.3 V Power Supply
Fast Access Time: 10, 12, 15 ns
Equal Address and Chip Enable Access Time
All Inputs and Outputs are TTL Compatible
Data Byte Control
Fully Static Operation
Power Operation: 140/135/130 mA Maximum, Active AC
Industrial Temperature Option: – 40 to + 85°C
Part Number: SCM6323AYJ10A
BLOCK DIAGRAM
G
OUTPUT
ENABLE
BUFFER
7
A
16
ADDRESS
BUFFERS
9
ROW
COLUMN
DECODER DECODER
8
HIGH BYTE OUTPUT ENABLE
LOW BYTE OUTPUT ENABLE
8
HIGH
BYTE
OUTPUT
BUFFER
HIGH
BYTE
WRITE
DRIVER
8 DQb
8
YJ PACKAGE
400 MIL SOJ
CASE 919–01
TS PACKAGE
44–LEAD
TSOP TYPE II
CASE 924A–02
Freescale Semiconductor, Inc...
PIN ASSIGNMENT
A
A
A
A
A
E
DQa
DQa
DQa
DQa
VDD
VSS
DQa
DQa
DQa
DQa
W
A
A
A
A
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
A
A
G
UB
LB
DQb
DQb
DQb
DQb
VSS
VDD
DQb
DQb
DQb
DQb
NC
A
A
A
A
NC
E
CHIP
ENABLE
BUFFER
64K x 16
BIT
MEMORY
ARRAY
16
SENSE
AMPS
8
8
W
WRITE
ENABLE
BUFFER
LOW
BYTE
OUTPUT
BUFFER
8
LOW
BYTE
WRITE
DRIVER
8 DQa
8
PIN NAMES
A . . . . . . . . . . . . . . . . . . . . . . . . Address Input
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
W . . . . . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
UB . . . . . . . . . . . . . . . . . . . . . . . . Upper Byte
LB . . . . . . . . . . . . . . . . . . . . . . . . . Lower Byte
DQa . . . . . . . . . . . . Lower Data Input/Output
DQb . . . . . . . . . . . . Upper Data Input/Output
VDD . . . . . . . . . . . . . . + 3.3 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . . No Connection
8
LB
UB
BYTE
ENABLE
BUFFER
HIGH BYTE WRITE ENABLE
LOW BYTE WRITE ENABLE
This document contains information on a new product under development. Motorola reserves the right
to change or discontinue this product without notice.
REV 5
11/4/98
©
Motorola, Inc. 1998
MOTOROLA FAST SRAM
For More Information On This Product,
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MCM6323A
1
Freescale Semiconductor, Inc.
TRUTH TABLE
(X = Don’t Care)
E
H
L
L
L
L
L
L
L
L
G
X
H
X
L
L
L
X
X
X
W
X
H
X
H
H
H
L
L
L
LB
X
X
H
L
H
L
L
H
L
UB
X
X
H
H
L
L
H
L
L
Mode
Not Selected
Output Disabled
Output Disabled
Low Byte Read
High Byte Read
Word Read
Low Byte Write
High Byte Write
Word Write
VDD Current
ISB1, ISB2
IDDA
IDDA
IDDA
IDDA
IDDA
IDDA
IDDA
IDDA
DQa
High–Z
High–Z
High–Z
Dout
High–Z
Dout
Din
High–Z
Din
DQb
High–Z
High–Z
High–Z
High–Z
Dout
Dout
High–Z
Din
Din
ABSOLUTE MAXIMUM RATINGS
(See Notes)
Rating
Symbol
VDD
Vin
Iout
PD
Commerial
Industrial
Commerial
Industrial
Tbias
TA
Tstg
Value
– 0.5 to + 4.6
– 0.5 to VDD + 0.5
±
20
0.75
– 10 to + 85
– 45 to + 90
0 to + 70
– 40 to + 85
– 55 to + 150
Unit
V
V
mA
W
°C
°C
°C
Freescale Semiconductor, Inc...
Supply Voltage
Voltage on Any Pin
Output Current per Pin
Package Power Dissipation
Temperature Under Bias
Operating Temperature
Storage Temperature
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid appli-
cation of any voltage higher than maximum
rated voltages to these high–impedance cir-
cuits.
This CMOS memory circuit has been de-
signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. All voltages are referenced to VSS.
3. Power dissipation capability will be dependent upon package characteristics and use
environment.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V
±
0.3 V, TA = 0 to 70°C, Unless Otherwise Noted)
(TA = – 40 to + 85°C for Industrial Temperature Offering)
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
VDD
VIH
VIL
Min
3.0
2.2
– 0.5
*
Typ
3.3
—
—
Max
3.6
VDD + 0.3
**
0.8
Unit
V
V
V
* VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width
≤
20 ns) for I
≤
20.0 mA.
** VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2.0 V ac (pulse width
≤
20 ns) for I
≤
20.0 mA.
DC CHARACTERISTICS
Parameter
Input Leakage Current (All Inputs, Vin = 0 to VDD)
Output Leakage Current (E = VIH, Vout = 0 to VDD)
Output Low Voltage
Output High Voltage
(IOL = + 4.0 mA)
(IOL = + 100
µA)
(IOH = – 4.0 mA)
(IOH = – 100
µA)
Symbol
Ilkg(I)
Ilkg(O)
VOL
VOH
Min
—
—
—
2.4
VDD – 0.2
Max
±
1.0
±
1.0
0.4
VSS + 0.2
—
Unit
µA
µA
V
V
MCM6323A
2
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MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
POWER SUPPLY CURRENTS
(See Note 1)
Parameter
AC Active Supply Current (Iout = 0 mA)
(VDD = Max, f = fmax)
AC Standby Current (E = VIH, VDD = Max,
f = fmax)
CMOS Standby Current (VDD = Max, f = 0 MHz,
E
≥
VDD – 0.2 V, Vin
≤
VSS + 0.2 V,
or
≥
VDD – 0.2 V)
Commerical
Industrial
Commerical
Industrial
Commerical
Industrial
Symbol
IDDA
ISB1
ISB2
6323A–10
140
150
40
45
5
5
6323A–12
135
140
35
40
5
5
6323A–15
130
135
30
35
5
5
Unit
mA
mA
mA
Notes
2
2
NOTES:
1. Typical current = 25°C @ 3.3 V.
2. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V, VIL = 0 V).
CAPACITANCE
(f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Address Input Capacitance
Symbol
Cin
Cin
CI/O
Typ
—
—
—
Max
6
6
8
Unit
pF
pF
pF
Freescale Semiconductor, Inc...
Control Input Capacitance
Input/Output Capacitance
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V
±
0.3 V, TA = 0 to +70°C, Unless Otherwise Noted)
(TA = – 40 to + 85°C for Industrial Temperature Offering)
Logic Input Timing Measurement Reference Level . . . . . . . . 1.50 V
Logic Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.50 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
READ CYCLE TIMING
(See Notes 1, 2, 3, and 4)
MCM6323A–10
Parameter
P
Read Cycle Time
Address Access Time
Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Enable Low to Output Active
Output Enable Low to Output Active
Enable High to Output High–Z
Output Enable High to Output High–Z
Byte Enable Access Time
Byte Enable Low to Output Active
Byte High to Output High–Z
Symbol
S b l
tAVAV
tAVQV
tELQV
tGLQV
tAXQX
tELQX
tGLQX
tEHQZ
tGHQZ
tBLQV
tBLQX
tBHQZ
Min
10
—
—
—
3
3
0
—
—
—
0
0
Max
—
10
10
4
—
—
—
4
4
4
—
5
MCM6323A–12
Min
12
—
—
—
3
3
0
—
—
—
0
0
Max
—
12
12
5
—
—
—
5
5
5
—
5
MCM6323A–15
Min
15
—
—
—
3
3
0
—
—
—
0
0
Max
—
15
15
6
—
—
—
6
6
6
—
5
Unit
U i
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6, 7, 8
6, 7, 8
6, 7, 8
6, 7, 8
6, 7, 8
6, 7, 8
6
Notes
N
5
NOTES:
1. W is high for read cycle.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. Device is continuously selected (E = VIL, G = VIL, and LB and/or UB = VIL).
4. Addresses valid prior to or coincident with E going low.
5. All read cycle timings are referenced from the last valid address to the first transitioning address.
6. Transition is measured 200 mV from steady–state voltage.
7. At any given voltage and temperature, tEHQZ (max) < tELQX (min), and tGHQZ (max) < tGLQX (min), both for a given device and from
device to device.
8. This parameter is sampled and not 100% tested.
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MCM6323A
3
Freescale Semiconductor, Inc.
OUTPUT
Z0 = 50
Ω
RL = 50
Ω
1.5 V
30 pF
Figure 1. Equivalent AC Test Load
2.0
1.5
DELTA TIME DELAY (ns)
1.0
Freescale Semiconductor, Inc...
OUTPUT
CL
0.5
0
– 0.5
0
20
40
60
80
100
LUMPED CAPACITANCE, CL (pF)
@ T = 25°C, VDD = 3.3 V
Figure 2. Lumped Capacitive Load and Typical Derating Curve
+ 0.3
+ 0.2
DELTA TIME DELAY (ns)
DELTA TIME DELAY (ns)
+ 0.1
0
– 0.1
– 0.2
– 0.3
3.0
3.1
3.2
3.3
3.4
3.5
3.6
OUTPUT
30 pF
+ 0.3
+ 0.2
+ 0.1
0
– 0.1
– 0.2
– 50 – 25
0
25
50
75
100
VDD (V)
@ T = 25°C
T (°C)
@ VDD = 3.3 V
Figure 3. Derating Across Temperature and Voltage
MCM6323A
4
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Freescale Semiconductor, Inc.
READ CYCLE 1
(See Note 7)
tAVAV
A (ADDRESS)
tAXQX
Q (DATA OUT)
PREVIOUS DATA VALID
tAVQV
DATA VALID
READ CYCLE 2
(See Note 8)
tAVAV
Freescale Semiconductor, Inc...
A (ADDRESS)
tAVQV
tELQV
E (CHIP ENABLE)
tELQX
G (OUTPUT ENABLE)
tGLQV
tGLQX
LB, UB (BYTE ENABLE)
tBLQV
tBLQX
Q (DATA OUT)
DATA VALID
tBHQZ
tGHQZ
tEHQZ
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MCM6323A
5
Embedded System
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