NJU3502
PRELIMINARY
4-BIT SINGLE CHIP MICRO CONTROLLER
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GENERAL DESCRIPTION
The
NJU3502
is the C-MOS 4-bit Single Chip Micro
Controller consisting of the 4-bit CPU Core, Input / Output
Selectable I/O ports, Program ROM, Data RAM, Timer, 8-
bit Serial Interface, and Oscillator Circuit (CR or Ceramic
or X'tal). It realizes the control for home appliances or
toys by only few external components.
The
NJU3502
is suitable for battery operated appliances
because of low operating current, wide operating voltage
range, and STANDBY function(HALT mode).
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PACKAGE OUTLINE
NJU3502L
NJU3502M
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FEATURES
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PIN CONFIGURATION
1
2
3
4
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6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
DD
PC1
PC0
PB3
PB2
PB1
PB0
SCK/CKOUT
SDI(O)/PF1
SDO/PF0
EXTI/PE0
RESET
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Internal Program ROM 1024 X 8 bits
PC2
Internal Data RAM
64 X 4 bits
PC3
Input / Output Port
17 lines(MAX)
10 lines Input / Output direction of each bit is
PD0
selected by the mask option.
PD1
4 lines
Input / Output direction of 4-bit lines group
can be changed by the program.
PA0
Additional functions by the mask option.
PA1
External Interrupt Terminal : EXTI/PE0
Serial Interface Terminals
PA2
: SDO/PF0, SDI(O)/PF1
PA3
High Output-Current terminal (4 lines)
N-Channel FET Open Drain Type (I
OL
)
TEST
15mA at V
DD
=5V
OSC1
Instruction Set
59 instructions
Subroutine Nesting
8 levels
OSC2
Pulse Edge Detector
V
SS
The rising or falling edge of a pulse is selected by
the mask option.
Instruction Executing Time
6/f
OSC
sec
Operating Frequency Range
30kHz
−
4MHz
Internal Oscillator
CR, or Ceramic, or X'tal oscillation and External clock input
STANDBY function (HALT mode)
Wide operating voltage range 2.4V
−
5.5V
8-bit Serial Input / Output port
Timer (8-bit re-load type timer)
Interrupt factor
3(external, timer, serial Input / Output)
C-MOS technology
Package outline
SDIP / DMP24
26/Mar/2001
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NJU3502
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BLOCK DIAGRAM
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NJU3502
Interrupt
V
DD
Logic
CPU CORE
V
SS
INT1
STACK
X Reg
Y Reg
AC
EXTI/PE0
TEST
RESET
TLU addr
X’ Reg
MUX
Y’ Reg
PC
INT2
TIMER
ROM
ALU
CPU
TIMING
GENERATOR
1024 x 8 bit
PRESCALER
OSC
OSC1
OSC2
INT3
SDO/PF0
IR
RAM
64 x 4 bits
ID
SDI(O)/PF1
SIO
STANDBY
CONTROLLER
SCK/CKOUT
PORT_A
∗3
∗1
PORT_B
∗2
∗1
PORT_C
∗3
∗1
PORT_D
∗1
∗3
∗1
Refer
!INPUT/OUTPUT
TERMINAL TYPE
∗2
Input / Output direction of 4-bit group is changed by the program.
∗3
Input / Output direction of each bit is selected by mask option.
PA0
PA1
PA2
PA3
PB0
PB1
PB2
PB3
PC0
PC1
PC2
PC3
PD0
PD1
NJU3502
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TERMINAL DESCRIPTION 1
No.
22
23
1
2
INPUT/OUTPUT
FUNCTION
INPUT/OUTPUT 4-bit Input / Output PORTC.
INPUT/OUTPUT Selects a terminal circuit for each port from follows by the
INPUT/OUTPUT mask option.
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C-MOS Input Terminal with Pull-up Resistance(IA)
INPUT/OUTPUT
•
C-MOS Input Terminal(IC)
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C-MOS Output Terminal(OB)
PD0
INPUT/OUTPUT 2-bit Input / Output PORTD.
PD1
INPUT/OUTPUT Selects a terminal circuit for each port from follows by the
mask option.
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C-MOS Schmitt Trigger Input Terminal with
Pull-up Resistance(IB)
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C-MOS Schmitt Trigger Input Terminal(ID)
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C-MOS Output Terminal(OB)
When the ports are selected as the input terminal, PD0
operates also as RESTART signal input terminal to return
from STANDBY mode, and PD1 operates also as the Edge
Detector Terminal.
PA0
INPUT/OUTPUT 4-bit Input / Output PORTA.
PA1
INPUT/OUTPUT Selects a terminal circuit for each port from follows by the
PA2
INPUT/OUTPUT mask option.
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C-MOS Input Terminal with Pull-up Resistance(IA)
PA3
INPUT/OUTPUT
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C-MOS Input Terminal(IC)
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C-MOS Output Terminal(OB)
TEST
INPUT
Maker Testing Terminal with Pull-down Resistance
The terminal is recommended to connect to GND.
OSC1
INPUT
Internal Oscillator Terminals.
OSC2
OUTPUT
Connects a device selected from the ceramic or the crystal
resonator, or the resistor, to these terminals for the internal
oscillator.
In the external clock operation, OSC1 is the external clock
input terminal and OSC2 is normally open terminal.
V
SS
–
Power Source (0V)
INPUT
RESET Terminal.
RESET
When the low level input-signal, the system is initialized.
EXTI / PE0
INPUT
1-bit Input PORTE.
Selects a function of either 1) or 2) for PORTE by the mask
option.
1) External Interrupt Input Terminal with Pull-up Resistance.
:EXTI
2) 1-bit Input Terminals as PORTE
Selects a terminal circuit for each port from follows by the
mask option.
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C-MOS Schmitt Trigger Input Terminal with
Pull-up Resistance(IB)
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C-MOS Schmitt Trigger Input Terminal(ID)
Note ) INPUT/OUTPUT : Input or Output is selected by the mask option.
INOUT
: Input or Output is changed by the program.
SYMBOL
PC0
PC1
PC2
PC3
3
4
5
6
7
8
9
10
11
12
13
14
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NJU3502
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TERMINAL DESCRIPTION 2
No.
SYMBOL
15 SDO
16
/ PF0
SDI(O)
/ PF1
FUNCTION
2-bit Input / Output PORTF.
Selects a function of either 1) or 2) for PORTF by the mask
option.
1) Serial Interface Function
Serial Data Output Terminal : SDO
Serial Data Input-Output Terminal with Pull-up
Resistance : SDI(O)
2) 2-bit Input / Output Terminals as PORTF.
Selects a terminal circuit for each port from follows by the mask
option.
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C-MOS Input Terminal with Pull-up Resistance (IA):PF1
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C-MOS Input Terminal(IC):PF1
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C-MOS Output Terminal(OB):PF0,PF1
SCK /
SCK :INOUT Selects a function of either 1) or 2) by the mask option.
CKOUT CKOUT :
1) Serial Clock Input or Output Terminal with Pull-up
OUTPUT
Resistance. :SCK
2) Clock Divided by Prescaler Output Terminal with Pull-up
Resistance. :CKOUT
Selects the dividing times of the clock in the prescaler by the
mask option.
PB0
INOUT
4-bit Programmable Input / Output PORTB
PB1
INOUT
These 4-bit terminals’ direction can be changed by the program
PB2
INOUT
as 4-Input or 4-Output.
PB3
INOUT
Use of Pull-up resistance is in accordance with the mask option.
•
as Input : C-MOS Input Terminals
•
as Output: Nch-FET Open-Drain Output Terminal
V
DD
–
Power source (2.4V
−
5.5V)
Note ) INPUT/OUTPUT : Input or Output is selected by the mask option.
INOUT
: Input or Output is changed by the program.
INPUT/OUTPUT
SDO :OUTPUT
PF0 :OUTPUT
SDI(O) :INOUT
PF1 :
INPUT/OUTPUT
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18
19
20
21
24
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NJU3502
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INTERNAL SYSTEM DESCRIPTION
The
NJU3502
is a C-MOS 4-Bit Single Chip Micro Controller consisted of Original CPU Core, Selectable
Input-Output(I/O) Ports(MAX. 17 lines), Program ROM(1024 bytes), Data RAM(64 nibbles), 8-bit Serial
Interface, 8-Bit Timer, Interrupt Control Circuit and Oscillator Circuit.
The CPU block in the
NJU3502
is consisted of ALU(Arithmetic Logic Unit) executing the binary adding,
subtracting or logical calculating, AC(Accumulator), four Registers, STACK allowing the 8-level subroutine-
nesting or Interrupt operation, PC(Program Counter) indicating 1024 addresses sequentially, and Timing
generator.
The
NJU3502
can be applied to the various markets because of the rich and efficient instruction set(59
instructions), wide operating voltage range(2.4V to 5.5V), low operating current, and STANDBY function
reducing the power supply current.
(1) INTERNAL REGISTER
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Accumulator(AC)
Accumulator(AC) is structured by the 4-bit register. It holds a data or a result of calculation, and
executes the shift-operation(ROTATE) or the data transference between the other registers and Data
Memory(RAM).
The accumulator condition is unknown on the “RESET” operation.
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X-register(X-reg)
X-register(X-reg) operates as the 4-bit register. Bit0 and bit1 of X-reg operate also as the RAM address
pointer with Y-register.
The X-reg condition is unknown on the “RESET” operation.
Y-register(Y-reg)
Y-register(Y-reg) operates as the 4-bit register or the RAM address pointer with bit1 and bit2 of X-reg.
The Y-reg condition is unknown on the “RESET” operation.
X'-register(X'-reg)
X'-register(X’-reg) operates as the 4-bit register or a part of Program Memory(ROM) address pointer for
looking data in the ROM(TRM instruction) up function.
The X’-reg condition is unknown on the “RESET” operation.
Y'-register(Y'-reg)
Y'-register(Y’-reg) operates as the 4-bit register or the peripheral register number(PHYn) pointer.
The Y’-reg condition is unknown on the “RESET” operation.
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(2) INTERNAL FLAG
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RPC flag(RPC)
RPC flag(RPC) changes the instruction table. Several instructions perform either of the dual tasks in
accordance with the RPC flag condition. The RPC flag condition selects either of two couples of registers
which are X- and Y-reg, or X'- and Y'-reg. X- or Y- reg is selected when the RPC flag condition is
"0"(RPC=0). X'- or Y'- reg is selected when the RPC flag condition is "1"(RPC=1). The RPC flag
condition is set to "1"(RPC=1) by SRPC instruction, and is set to “0”(RPC=0) by RRPC instruction.
The RPC flag condition is set to “0” on the “RESET” operation.
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CARRY flag(CY)
When the carry occurs after the adding calculation, the CY flag condition is set to "1"(CY=1), and when
no carry, the CY flag condition is set to "0"(CY=0). When the borrow occurs after the subtracting
calculation, the CY flag condition is set to "0"(CY=0), and when no borrow, the CY flag condition is set to
"1"(CY=1). The bit-operation instruction operates the bit data rotation on the CY flag combined with the
Accumulator or the other register.
The CY flag condition is set to "1"(CY=1) by SEC instruction and is set to "0"(CY=0) by CLC instruction.
The CY flag condition is kept until the end of the next instruction executing cycle. The CY flag condition is
unknown on the “RESET” operation.
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