EEWORLDEEWORLDEEWORLD

Part Number

Search

DPS2ME16MKI3-45M

Description
SRAM Module, 2MX16, 45ns, CMOS
Categorystorage    storage   
File Size498KB,8 Pages
ManufacturerTwilight Technology Inc.
Download Datasheet Parametric View All

DPS2ME16MKI3-45M Overview

SRAM Module, 2MX16, 45ns, CMOS

DPS2ME16MKI3-45M Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerTwilight Technology Inc.
package instruction,
Reach Compliance Codeunknown
ECCN code3A001.A.2.C
Maximum access time45 ns
Spare memory width8
JESD-30 codeR-XQMA-P52
memory density33554432 bit
Memory IC TypeSRAM MODULE
memory width16
Number of functions1
Number of terminals52
word count2097152 words
character code2000000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize2MX16
Package body materialUNSPECIFIED
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal formPIN/PEG
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
2Mx16, 20 - 45ns, STACK
30A129-28
B
32 Megabit High Speed CMOS SRAM
DESCRIPTION:
The DPS2ME16MKn3 High Speed SRAM ‘’STACK’’ modules are a
revolutionary new memory subsystem using Dense-Pac
Microsystems’ ceramic Stackable Leadless Chip Carriers (SLCC).
Available in straight leaded, ‘’J’’ leaded or gullwing leaded
packages. The module packs 32-Megabits of low-power CMOS
static RAM in an area as small as 0.549 in
2
, while maintaining a
total height as low as 0.545 inches.
The DPS2ME16MKn3 STACK modules contain eight individual
512K x 8 SRAMs, each packaged in a hermetically sealed SLCC,
making the modules suitable for commercial, industrial and military
applications.
By using SLCCs, the ‘’Stack’’ family of modules offer a higher board
density of memory than available with conventional through-hole,
surface mount or hybrid techniques.
SLCC Stack
DPS2ME16MKn3
Straight
Leaded
Stack
FEATURES:
Organizations Available:
2 Meg x 16 or 4 Meg x 8
Access Times:
20*, 25, 30, 35, 45ns
Fully Static Operation - No clock or refresh required
Single +5V Power Supply,
±
10% Tolerance
TTL Compatible
Common Data Inputs and Outputs
Low Data Retention Voltage:
2.0V min.
Packages Available:
SLCC Stack
Straight Leaded Stack
‘’J’’ Leaded Stack
Gullwing Leaded Stack
‘’J’’ Leaded
Stack
*
Commercial and Industrial Grade only.
Gullwing
Leaded
Stack
FUNCTIONAL BLOCK DIAGRAM
PIN NAMES
A0 - A18
I/O0 - I/O15
CE0 - CE3
WE0, WE1
OE0, OE1
V
DD
V
SS
N.C.
30A129-28
REV. B
This document contains information on a product presently under
development at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right
to change products or specifications herein without prior notice.
Address Inputs
Data Input/Output
Low Chip Enables
Write Enables
Output Enables
Power (+5V)
Ground
No Connect
1
wince looking for a master to teach me how to get started
I'm a beginner in wince, and I hope that an expert can give me some pointers. Please be specific. Don't read books for every sentence. It's useless. I just want to get started quickly....
apple0731 Embedded System
Does anyone have any opinions on question A?
Let's talk about it, let's exchange ideas...
poseidonw MCU
Play "Two Tigers" through the mini2440 buzzer
The program simulates the seven notes of music (do, re, me, fa, so, la, si), including bass, middle and treble. Friends who are interested can download the program to the target board to try it out, o...
xyz.eeworld Embedded System
How to burn u-boot and uClinux?
I compiled u-boot in Linux system to generate three files: u-boot, u-boot.bin and u-boot.srec. I compiled uClinux (version 2.4.x) to generate image.ram, image.rom and romfs.img. What tools should I us...
susion Linux and Android
The footprints of an electronics major worth learning from
[i=s]This post was last edited by paulhyde on 2014-9-15 09:30[/i]I have been in the school's Electronic Innovation Laboratory for six years at Harbin Engineering University. During these four years, t...
wonderto Electronics Design Contest
How does the scanning time of each pixel of a VGA monitor come from 25ns (800*600*60hz)?
[i=s] This post was last edited by 调戏、和尚/ on 2015-7-22 16:59 [/i] When using FPGA to scan a VGA display, the tutorial says that the scan time for each pixel is 25ns (based on 800*600*60hz). How did th...
调戏、和尚/ FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1249  2929  2330  2885  2452  26  59  47  50  54 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号