CY2210
133-MHz Spread Spectrum Clock Synthesizer/Driver
with AGP, USB, and DRCG Support
Features
• Mixed 2.5V and 3.3V Operation
• Compliant to Intel® CK133 (CY2210-3) & CK133W
(CY2210-2) synthesizer and driver specification
• Multiple output clocks at different frequencies
— Four CPU clocks, up to 133 MHz
— Eight synchronous PCI clocks, 1 free-running
— Two CPU/2 clocks, at one-half the CPU frequency
— Four AGP clocks at 66 MHz
— Three synchronous APIC clocks, at 16.67 MHz
— One USB clock at 48 MHz
— Two reference clocks at 14.318 MHz
• Spread Spectrum clocking
— 32.5-kHz modulation frequency @ 133 MHz
— 33.1-kHz modulation frequency @ 100 MHz for
CY2210-02/03
— 33.4-kHz modulation frequency @ 100 MHz for
CY2210-04
— EPROM programmable percentage of spreading.
Default is –0.6%, which is recommended by Intel
• Power-down features
• Three Select inputs
• Low-skew and low-jitter outputs
• OE and Test Mode support
• 56-pin SSOP package
Benefits
Usable with Pentium
II and Pentium
III processors
Single-chip main motherboard clock generator
— Driven together, support 4 CPUs and a chipset
— Support for 4 PCI slots and chipset
— Drives up to two main memory clock generators, includ-
ing DRCG (CPUCLK/2)
— Support for multiple AGP slots
— Support multiprocessing systems
— Supports USB frequencies and I/O chip
Enables reduction of EMI in some systems
Supports mobile systems
Supports up to eight CPU clock frequencies
Meets tight system timing requirements at high frequency
Enables ATE and “bed of nails” testing
Widely available, standard package enables lower cost
SSOP
Top View
REFCLK [0–1] (14.318 MHz)
V
SSREF
REFCLK0
REFCLK1
V
DDREF
XTALIN
XTALOUT
V
SSPCI
1
2
3
4
5
6
7
8
56
55
54
53
52
51
50
49
V
DDAPIC
APICCLK2
APICCLK1
APICCLK0
V
SSAPIC
V
DDCPU/2
CPUCLK/2
(DRCG)
Logic Block Diagram
CPUCLK [0–3]
CPU_STOP
XTALIN
XTALOUT
14.318
MHz
OSC.
CY2210-2/-3/-4
CPU
PLL
SEL1
SEL0
SEL133
SPREAD
PCI_STOP
PWR_DWN
Divider,
EPROM-Pr
ogDelay
and
Stop Logic
CPUCLK/2 [0–1] (DRCG)
PCICLK_F (33.33 MHz)
PCICLK [1–7] (33.33 MHz)
APICCLK [0–2] (16.67 MHz)
AGPCLK [0–3] (66.67 MHz)
PCICLK_F
PCICLK1
V
DDPCI
PCICLK2
PCICLK3
V
SSPCI
PCICLK4
PCICLK5
V
DDPCI
PCICLK6
PCICLK7
V
SSPCI
V
SSAGP
AGPCLK0
AGPCLK1
V
DDAGP
V
SSAGP
AGPCLK2
AGPCLK3
V
DDAGP
SEL133
CPUCLK/2
(DRCG)
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
V
SSCPU/2
V
DDCPU
CPUCLK3
CPUCLK2
V
SSCPU
V
DDCPU
CPUCLK1
CPUCLK0
V
SSCPU
AV
DD
AV
SS
PCI_STOP
CPU_STOP
PWR_DWN
SPREAD
SEL1
SEL0
V
DDUSB
USBCLK
V
SSUSB
EPROM
SYS
PLL
USBCLK (48 MHz)
Intel and Pentium are registered trademarks of Intel Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
May 18, 2000, rev. *A
CY2210
Pin Summary
Name
V
SSREF
V
DDREF
V
SSPCI
V
DDPCI
V
SSAGP
V
DDAGP
V
SSUSB
V
DDUSB
V
SSCPU
V
DDCPU
V
SSCPU
/2
V
DDCPU
/2
V
SSAPIC
V
DDAPIC
AV
SS
AV
DD
XTALIN
[1]
XTALOUT
[1]
CPUCLK [0–3]
PCICLK [1–7]
PCICLK_F
CPUCLK/2
AGPCLK [0–3]
APICCLK [0–2]
REFCLK [0–1]
USBCLK
CPU_STOP
PCI_STOP
PWR_DWN
SPREAD
SEL1
SEL0
SEL133
Pins
1
4
7, 13, 19
10, 16
20, 24
23, 27
29
31
40, 44
43, 47
48
51
52
56
38
39
5
6
41, 42, 45, 46
9, 11, 12, 14, 15, 17, 18
8
49, 50
21, 22, 25, 26
53, 54, 55
2, 3
30
36
37
35
34
33
32
28
Description
3.3V Reference ground
3.3V Reference voltage supply
3.3V PCI ground
3.3V PCI voltage supply
3.3V AGP ground
3.3V AGP voltage supply
3.3V USB ground
3.3V USB voltage supply
2.5V CPU ground
2.5V CPU voltage supply
2.5V CPU/2 ground
2.5V CPU/2 voltage supply
2.5V APIC ground
2.5V APIC voltage supply
Analog ground to PLL and Core
Analog voltage supply to PLL and Core
Reference crystal input
Reference crystal feedback
CPU clock outputs
PCI clock outputs, synchronously running at 33.33 MHz
Free running PCI clock
CPU/2 clock outputs, drive memory clock generator
AGP clock outputs, running at 66.66 MHz
APIC clock outputs, running at 16.67 MHz
Reference clock outputs, 14.318 MHz
48-MHz USB clock output
Active LOW input, disables CPU and AGP clocks when asserted
Active LOW input, disables PCI clocks when asserted
Active LOW input, powers down part when asserted
Active LOW input, enables spread spectrum when asserted
CPU frequency select input (See Function Table)
CPU frequency select input (See Function Table)
CPU frequency select input (See Function Table)
Note:
1. For best accuracy, use a parallel-resonant crystal, C
LOAD
= 18 pF. For crystals with different C
LOAD
, please refer to the application note, “Crystal Oscillator
Topics.”
2
CY2210
Function Table
[2]
SEL133
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
SEL1
0
1
0
1
0
1
0
1
SEL0
CPUCLK
(MHz)
Hi-Z
100.227
100
100
TCLK/2
N/A
133.33
133.33
[3]
CPUCLK/2
(MHz)
Hi-Z
50.114
50
50
TCLK/4
N/A
66.67
66.67
[3]
AGPCLK
(MHz)
Hi-Z
66.818
66.67
66.67
TCLK/4
N/A
66.67
66.67
[3]
PCICLK
(MHz)
Hi-Z
33.409
33.33
33.33
TCLK/8
N/A
33.33
33.33
[3]
USBCLK
(MHz)
Hi-Z
48.008
OFF
48
TCLK/2
N/A
OFF
48
[3]
REFCLK
(MHz)
Hi-Z
14.318
14.318
14.318
TCLK
N/A
14.318
14.318
[3]
APICCLK
(MHz)
Hi-Z
16.705
[3]
16.67
16.67
TCLK/16
N/A
16.67
16.67
Actual Clock Frequency Values
Target
Frequency
(MHz)
-2
100.0
133.33
48.0
-3
100.0
133.33
48.0
-4
100.0
133.33
48.0
-2
99.126
132.769
48.008
Actual
Frequency
(MHz)
-3
99.126
132.769
48.008
-4
100.227
132.769
48.008
-2
–8740
–4208
167
PPM
-3
–8740
–4208
167
-4
+2714
–4208
167
Clock
Output
CPUCLK
CPUCLK
USBCLK
Clock Enable Configuration
CPU_STOP
X
0
0
1
1
PWR_DWN
0
1
1
1
1
PCI_STOP
X
0
1
0
1
CPUCLK
LOW
LOW
LOW
ON
ON
CPUCLK/2
LOW
ON
ON
ON
ON
AGP
LOW
LOW
LOW
ON
ON
PCI
LOW
LOW
ON
LOW
ON
PCI_F
LOW
ON
ON
ON
ON
REF
APIC
LOW
ON
ON
ON
ON
OSC.
OFF
ON
ON
ON
ON
VCOs
OFF
ON
ON
ON
ON
Clock Driver Impedances
Impedance
Buffer Name
CPU, CPU/2, APIC
USB, REF
PCI, AGP
V
DD
Range
2.375–2.625
3.135–3.465
3.135–3.465
Buffer Type
Type 1
Type 3
Type 5
Minimum
Ω
13.5
20
12
Typical
Ω
29
40
30
Maximum
Ω
45
60
55
Notes:
2. TCLK is a test clock driven in on the XTALIN input in test mode.
3. Only CY2210-2 supports this option. In CY2210-3, this selection is defined as “N/A” or “Reserved”.
3
CY2210
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Supply Voltage ..................................................–0.5 to +7.0V
Input Voltage .............................................. –0.5V to V
DD
+0.5
Storage Temperature (Non-Condensing) ... –65°C to +150°C
Max. Soldering Temperature (10 sec) ...................... +260°C
Junction Temperature ............................................... +150°C
Package Power Dissipation .............................................. 1W
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................. >2000V
Operating Conditions
Over which Electrical Parameters are Guaranteed
Parameter
V
DDREF
, V
DDPCI
, AV
DD
,
V
DDAGP
V
DDUSB
,
V
DDCPU
, V
DDCPU/2
V
DDAPIC
T
A
C
L
Description
3.3V Supply Voltages
CPU and CPU/2 Supply Voltage
APIC Supply Voltage
Operating Temperature, Ambient
Max. Capacitive Load on
CPUCLK, CPUCLK/2, USBCLK, REF, APIC
PCICLK, AGP
Reference Frequency, Oscillator Nominal Value
14.318
Min.
3.135
2.375
2.375
0
Max.
3.465
2.625
2.625
70
20
30
14.318
MHz
Unit
V
V
V
°C
pF
f
(REF)
Electrical Characteristics
Over the Operating Range
Parameter
V
IH
V
IL
V
OH
V
OL
I
IH
I
IL
I
OH
Description
High-level Input Voltage
Low-level Input Voltage
Test Conditions
Except Crystal Pads. Threshold voltage for crystal pads = V
DD
/2
Except Crystal Pads
I
OH
= –1 mA
I
OH
= –1 mA
I
OL
= 1 mA
I
OL
= 1 mA
USB, REF, PCI, AGP
Low-level Output Voltage
[4]
CPU, CPU/2, APIC
USB, REF, PCI, AGP
Input High Current
Input Low Current
0 < V
IN
< V
DD
0 < V
IN
< V
DD
V
OH
= 2.0V
V
OH
= 2.0V
V
OH
= 2.4V
V
OH
= 2.4V
V
OL
= 0.4V
V
OL
= 0.4V
V
OL
= 0.4V
V
OL
= 0.4V
–16
–20
–15
19
25
10
20
APIC
USB, REF
AGP, PCI
I
OL
Low-level Output Current
[4]
CPU, CPU/2
APIC
USB, REF
AGP, PCI
I
OZ
I
DD2
I
DD3
I
DDPD2
I
DDPD3
Output Leakage Current
Three-state
Min. Max. Unit
2.0
0.8
2.0
2.4
0.4
0.4
10
10
–60
–72
–51
49
58
24
49
10
90
160
100
200
µA
mA
mA
µA
µA
mA
µA
µA
mA
V
V
V
V
High-level Output Voltage
[4]
CPU, CPU/2, APIC
High-level Output Current
[4]
CPU, CPU/2
–30 –100
2.5V Power Supply Current AV
DD
/V
DD33
= 3.465V, V
DD25
= 2.625V, F
CPU
= 133 MHz
3.3V Power Supply Current AV
DD
/V
DD33
= 3.465V, V
DD25
= 2.625V, F
CPU
= 133 MHz
2.5V Shutdown Current
3.3V Shutdown Current
AV
DD
/V
DD33
= 3.465V, V
DD25
= 2.625V
AV
DD
/V
DDQ3
= 3.465V, V
DD25
= 2.625V
Note:
4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
4
CY2210
Switching Characteristics
[4, 5]
Over the Operating Range
Parameter
t
1
t
2
t
2
t
2
t
3
t
3
t
3
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
All
CPU, CPU/2,
APIC
USB, REF
PCI, AGP
CPU, CPU/2,
APIC
USB, REF
PCI, AGP
CPU
CPU/2
APIC
AGP
PCI
CPU, AGP
AGP, PCI
CPU, APIC
CPU, PCI
CPU
CPU
CPU
CPU/2
APIC
USB
AGP
REF
CPU, PCI
Output
Description
Output Duty Cycle
[6]
Rising Edge Rate
Rising Edge Rate
Rising Edge Rate
Falling Edge Rate
Falling Edge Rate
Falling Edge Rate
CPU-CPU Skew
CPU/2-CPU/2 Skew
APIC-APIC Skew
AGP-AGP Skew
PCI-PCI Skew
CPU-AGP Clock Skew
AGP-PCI Clock Skew
CPU-APIC Clock Skew
CPU-PCI Clock Skew
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Settle Time
CPU and PCI clock stabilization from
power-up
t
1A
/t
1B
Between 0.4V and 2.0V
Between 0.4V and 2.4V
Between 0.4V and 2.4V
Between 2.0V and 0.4V
Between 2.4V and 0.4V
Between 2.4V and 0.4V
Measured at 1.25V
Measured at 1.25V
Measured at 1.25V
Measured at 1.5V
Measured at 1.5V
CPU leads. Measured at 1.25V for
2.5V clocks and 1.5V for 3.3V clocks
AGP leads. Measured at 1.5V
CPU leads. Measured at 1.25V
CPU leads. Measured at 1.25V clocks
and 1.5V for 3.3V clocks
With all outputs running (CY2210-2)
With all outputs running
(CY2210-3/-4)
With the USB output turned off
(CY2210-3/-4)
0
1.5
1.5
1.5
Test Conditions
Min.
45
1.0
0.5
1.0
1.0
0.5
1.0
Max.
55
4.0
2.0
4.0
4.0
2.0
4.0
175
175
250
250
500
1.5
4.0
4
4
150
250
200
250
500
500
500
1000
3
Unit
%
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
ps
ps
ps
ps
ps
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ms
Notes:
5. All parameters specified with loaded outputs.
6. Duty cycle is measured at 1.5V when V
DD
= 3.3V. When V
DD
= 2.5V, duty cycle is measured at 1.25V.
5
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