ADF4151 datasheet, PDF - EEWORLD Datasheet

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ADF4151: DescriptionPHASE LOCKED LOOP, 3500 MHz, QCC32; Categorysemiconductor Analog mixed-signal IC; File Size471KB，28 Pages; ManufacturerADI; Websitehttps://www.analog.com

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ADF4151 Overview

PHASE LOCKED LOOP, 3500 MHz, QCC32

ADF4151 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	32
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	5.5 V
Minimum supply/operating voltage	3 V
Rated supply voltage	3.3 V
Processing package description	5 X 5 MM, ROHS COMPLIANT, MO-220WHHD, LFCSP-32
state	ACTIVE
Craftsmanship	BICMOS
packaging shape	SQUARE
Package Size	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
surface mount	Yes
Terminal form	NO LEAD
Terminal spacing	0.5000 mm
Terminal location	QUAD
Packaging Materials	UNSPECIFIED
Temperature level	INDUSTRIAL
Analog IC other types	PHASE LOCKED LOOP

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Data Sheet

FEATURES

Fractional-N/Integer-N PLL Synthesizer

ADF4151

GENERAL DESCRIPTION

The

ADF4151

allows implementation of fractional-N or

integer-N phase-locked loop (PLL) frequency synthesizers

if used with an external voltage controlled oscillator (VCO),

loop filter, and external reference frequency.

The

ADF4151

is used with external VCO parts and is footprint

and software compatible with the

ADF4350.

The part consists

of a low noise digital phase frequency detector (PFD), a precision

charge pump, and a programmable reference divider. There is

a Σ-Δ based fractional interpolator to allow programmable

fractional-N division. The INT, FRAC, and MOD registers

define an overall N divider [N = (INT + (FRAC/MOD))]. The

RF output phase is programmable for applications that require

a particular phase relationship between the output and the

reference. The

ADF4151

also features cycle slip reduction

circuitry, leading to faster lock times without the need for

modifications to the loop filter.

Control of all the on-chip registers is through a simple 3-wire

interface. The device operates with a power supply ranging

from 3.0 V to 3.6 V that can be powered down when not in use.

The

ADF4151

is available in a 5 mm × 5 mm package.

Fractional-N synthesizer and integer-N synthesizer

RF bandwidth to 3.5 GHz

3.0 V to 3.6 V power supply

1.8 V logic compatibility

Separate charge pump supply (V

) allows extended tuning

voltage (up to 5.5 V) in 3 V systems

Programmable dual-modulus prescaler of 4/5 or 8/9

Programmable RF output phase

3-wire serial interface

Analog and digital lock detect

Switched bandwidth fast lock mode

Cycle slip reduction

APPLICATIONS

Wireless infrastructure (W-CDMA, TD-SCDMA, WiMax, GSM,

PCS, DCS, DECT)

Test equipment

Wireless LANs, CATV equipment

Clock generation

FUNCTIONAL BLOCK DIAGRAM

SDV

SET

REF

×2

DOUBLER

10-BIT R

COUNTER

÷2

DIVIDER

LOCK

DETECT

MULTIPLEXER

MUXOUT

SWITCH

CLK

DATA

DATA REGISTER

FUNCTION

LATCH

PHASE

COMPARATOR

CHARGE

PUMP

OUT

INTEGER

REG

FRACTION

REG

MODULUS

REG

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

N COUNTER

–

GND

Figure 1.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

10265-001

ADF4151

ADF4151

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings ............................................................ 6

Transistor Count ........................................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 9

Circuit Description ......................................................................... 11

Reference Input Section ............................................................. 11

RF N Divider ............................................................................... 11

INT, FRAC, MOD, and R Counter Relationship.................... 11

INT N Mode ................................................................................ 11

R Counter .................................................................................... 11

Phase Frequency Detector (PFD) and Charge Pump ............ 11

MUXOUT and Lock Detect ...................................................... 12

Input Shift Registers ................................................................... 12

Program Modes .......................................................................... 12

Data Sheet

Initialization Sequence .............................................................. 19

RF Synthesizer—A Worked Example ...................................... 20

Modulus ....................................................................................... 20

Reference Doubler and Reference Divider ............................. 20

12-Bit Programmable Modulus ................................................ 20

Cycle Slip Reduction for Faster Lock Times ........................... 21

Spurious Optimization and Fast lock ...................................... 21

Fast Lock Timer and Register Sequences ................................ 21

Fast Lock—An Example ............................................................ 22

Fast Lock—Loop Filter Topology............................................. 22

Spur Mechanisms ....................................................................... 22

Spur Consistency and Fractional Spur Optimization ........... 23

Phase Resync ............................................................................... 23

Applications Information .............................................................. 24

Direct Conversion Modulator .................................................. 24

Interfacing ................................................................................... 25

PCB Design Guidelines for Chip Scale Package .................... 25

Outline Dimensions ....................................................................... 26

Ordering Guide .......................................................................... 26

REVISION HISTORY

12/11—Rev. A to Rev. B

Changes to Normalized 1/f Noise Parameter, Table 1 ................. 4

11/11—Rev. 0 to Rev. A

Changes to Figure 28 ...................................................................... 23

10/11—Revision 0: Initial Version

Rev. B | Page 2 of 28

ADF4151 Related Products

	ADF4151	EVAL-ADF4151EB1Z
Description	PHASE LOCKED LOOP, 3500 MHz, QCC32	PHASE LOCKED LOOP, 3500 MHz, QCC32
Number of functions	1	1
Number of terminals	32	32
Maximum operating temperature	85 Cel	85 Cel
Minimum operating temperature	-40 Cel	-40 Cel
Maximum supply/operating voltage	5.5 V	5.5 V
Minimum supply/operating voltage	3 V	3 V
Rated supply voltage	3.3 V	3.3 V
Processing package description	5 X 5 MM, ROHS COMPLIANT, MO-220WHHD, LFCSP-32	5 X 5 MM, ROHS COMPLIANT, MO-220WHHD, LFCSP-32
state	ACTIVE	ACTIVE
Craftsmanship	BICMOS	BICMOS
packaging shape	SQUARE	SQUARE
Package Size	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
surface mount	Yes	Yes
Terminal form	NO LEAD	NO LEAD
Terminal spacing	0.5000 mm	0.5000 mm
Terminal location	QUAD	QUAD
Packaging Materials	UNSPECIFIED	UNSPECIFIED
Temperature level	INDUSTRIAL	INDUSTRIAL
Analog IC other types	PHASE LOCKED LOOP	PHASE LOCKED LOOP

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