EDI8L32256C
Features
256Kx32 bit CMOS Static
DSP Memory Solution
Texas Instruments TMS320C3x, TMS320C4x
Analog SHARC
TM
DSP
Motorola DSP96002
Random Access Memory Array
Fast Access Times: 15, 17, 20 and 25ns
Individual Byte Enables
User Configurable Organization
with Minimal Additional Logic
Master Output Enable and Write Control
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
Surface Mount Package
68 Lead PLCC, No. 99, JEDEC MO-47AE
Small Footprint, 0.990 Sq. In.
Multiple Ground Pins for Maximum
Noise Immunity
Single +5V (±5%) Supply Operation
256Kx32, 5V Static Ram
The EDI8L32256C is a high speed, 5V, 8 megabit SRAM.
The device is available with access times of 15, 17, 20 and
25ns, allowing the creation of a no wait state DSP memory
solution.
The device can be configured as a 256Kx32 and used to
create a single chip external data memory solution for
Texas Instruments' TMS320C30/31 (figure 3), TMS
320C32 (figure 4) or TMS320C4x (figure 5), Motorola's
DSP96002 and Analog Device's SHARC
TM
DSP (figure 6).
Alternatively the device's chip enables can be used to
configure it as a 512Kx16. A 512Kx48 program memory
array for Analog's SHARC
TM
DSP is created using three
devices (figure 7). If this memory is too deep, two 256Kx24s
(EDI8L24256C) can be used to create a 256Kx48 array or
two 128Kx24s (EDI8L24128C) can be used to create a
128Kx48 array.
The device provides a 32% space savings when com-
pared to two monolithic 256Kx16, 44 pin SOJs.
The device provides a memory upgrade of the
EDI8L32128C (128Kx32) and the EDI8L3265C (64Kx32).
For more memory the device can be upgraded to the
EDI8L32512C (512Kx32). For additional upgrade infor-
mation see figure 8.
NOTE: Solder Reflow temperature should not exceed 230°C for 10 seconds.
Pin Configurations and Block Diagram
Note: For memory upgrade information refer to page 8,
Figure 8 "EDI MCM-L upgrade path".
February 1999 Rev. 5
ECO# 11254
T
NO
D
DE
EN
M
M
CO
RE
1
Pin Names
AØ-A17
EØ-E1
BSØ-BS3
W
G
DQØ-DQ31
VCC
VSS
NC
R
FO
Address Inputs
Chip Enables (One per Word)
Byte Selects (One per Byte)
Master Write Enable
Master Output Enable
Common Data Input/Output
Power (+5V±5%)
Ground
No Connection
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
W
NE
GN
SI
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EDI8L32256C
Absolute Maximum Ratings*
Voltage on any pin relative to VSS
Operating Temperature TA (Ambient)
Commercial
Industrial
Storage Temperature
Power Dissipation
Output Current.
Junction Temperature, TJ
-0.5V to 7.0V
0°C to + 70°C
-40°C to +85°C
-55°C to +125°C
3 Watts
20 mA
175°C
Recommended DC Operating Conditions
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Sym
VCC
VSS
VIH
VIL
Min
4.75
0
2.2
-0.3
Typ
5.0
0
--
--
Max
Units
5.25
V
0
V
VCC+0.5 V
0.8
V
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
VSS to 3.0V
5ns
1.5V
Figure 1
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
(note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF)
DC Electrical Characteristics
Parameter
Operating Power Supply Current
Standby (TTL) Supply Current
Full StandbySupply Current
Input Leakage Current
Output Leakage Current
Output High Volltage
Output Low Voltage
Sym
ICC1
ICC2
ICC3
ILI
ILO
VOH
VOL
Conditions
W= VIL, II/O = 0mA,
Min Cycle
E
³
VIH, VIN
£
VIL or
VIN
³
VIH, f=ØMHz
E
³
VCC-0.2V
VIN
³
VCC-0.2V or
VIN
£
0.2V
VIN = 0V to VCC
V I/O = 0V to VCC
IOH = -4.0mA
IOL = 8.0mA
Min
Max
15/17
575
120
20
±10
±10
0.4
20/25
480
120
20
Units
mA
mA
mA
µA
µA
V
V
2.4
Truth Table
E
H
L
L
L
L
W
X
H
X
H
L
G BSØ-3
Mode
X
X
Standby
H
X
Output Disable
X
H Output Disable
L
L
Read
X
L
Write
Output
High Z
High Z
High Z
DOUT
DIN
Power
ICC2, ICC3,
ICC1
ICC1
ICC1
ICC1
Capacitance
(f=1.0MHz, VIN=VCC or VSS)
Parameter
Address Lines
Data Lines
Write & Output Enable Lines
Chip Enable Lines/Byte Select
Sym
CA
CD/Q
W, G
E, BS
Max
20
10
6
9
Unit
pF
pF
pF
pF
X Means Don't Care
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2
EDI8L32256C
AC Characteristics Read Cycle
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Byte Select Access Time
Chip Enable to Output in Low Z (1)
Byte Select to Output in Low Z
Chip Disable to Output in High Z (1)
Byte Select to Output in High Z
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
Symbol
JEDEC
Alt.
TAVAV TRC
TAVQV TAA
TELQV TACS
TBLQX TBLZ
TELQX TCLZ
TBLQX TBLZ
TEHQZ TCHZ
TBHQZ TBHZ
TAVQX TOH
TGLQV TOE
TGLQX TOLZ
TGHQZ TOHZ
15ns
Min Max
15
15
15
15
3
3
8
8
3
6
2
5
17ns
Min Max
17
17
17
17
3
3
8
8
3
8
2
6
20ns
Min Max
20
20
20
20
3
3
10
10
3
10
2
8
25ns
Min Max
25
25
25
25
3
3
10
10
3
10
2
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle 1 - W High, G, E Low
Read Cycle 2 - W High
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI8L32256C
AC Characteristics Write Cycle
Parameter
Write Cycle Time
Chip Enable to End of Write
Byte Select to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
Output Active from End of Write (1)
Note 1: Parameter guaranteed, but not tested.
Symbol
JEDEC
Alt.
TAVAV TWC
TELWH TCW
TELEH TCW
TBLWH TBW
TAVWL
TAS
TAVEL
TAS
TAVWH TAW
TAVEH TAW
TWLWH TWP
TWLEH TWP
TWHAX TWR
TEHAX TWR
TWHDX TDH
TEHDX
TDH
TWLQZ TWHZ
TDVWH TDW
TDVEH TDW
TWHQX TWLZ
15ns
17ns
20ns
25ns
Min Max Min Max Min Max Min Max Units
15
17
20
25
ns
9
10
15
20
ns
9
10
15
20
ns
9
10
15
20
ns
0
0
0
0
ns
0
0
0
0
ns
10
12
15
15
ns
10
12
15
15
ns
10
12
15
15
ns
10
12
15
15
ns
0
0
0
0
ns
0
0
0
0
ns
0
0
0
0
ns
0
0
0
0
ns
0
6
0
7
0 7 0
10 ns
6
8
8
12
ns
6
8
8
12
ns
2
2
2
2
ns
Write Cycle 1 - W Controlled
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4
Test/Measurement
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