CY7C374-66GC datasheet, PDF - EEWORLD Datasheet

CY7C374-66GC: DescriptionFlash PLD, 20ns, 128-Cell, CMOS, CPGA84, CAVITY UP, PGA-84; CategoryProgrammable logic devices Programmable logic; File Size410KB，12 Pages; ManufacturerCypress Semiconductor

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CY7C374-66GC Overview

Flash PLD, 20ns, 128-Cell, CMOS, CPGA84, CAVITY UP, PGA-84

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	PGA
package instruction	CAVITY UP, PGA-84
Contacts	84
Reach Compliance Code	compliant
Other features	LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 4 EXTERNAL CLOCKS; SHARED INPUT/CLOCK
maximum clock frequency	50 MHz
In-system programmable	NO
JESD-30 code	S-CPGA-P84
JESD-609 code	e0
JTAG BST	NO
length	29.464 mm
Dedicated input times	2
Number of I/O lines	64
Number of macro cells	128
Number of terminals	84
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2 DEDICATED INPUTS, 64 I/O
Output function	MACROCELL
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Encapsulate equivalent code	PGA84M,11X11
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	FLASH PLD
propagation delay	20 ns
Certification status	Not Qualified
Maximum seat height	4.3688 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED
width	29.464 mm

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