DS4550E+ datasheet, PDF - EEWORLD Datasheet

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DS4550E+: Description9 I/O, PIA-GENERAL PURPOSE, PDSO20, TSSOP-20; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，19 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/; Environmental Compliance

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DS4550E+ Overview

9 I/O, PIA-GENERAL PURPOSE, PDSO20, TSSOP-20

DS4550E+ Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Rochester Electronics
Parts packaging code	TSSOP
package instruction	TSSOP,
Contacts	20
Reach Compliance Code	unknown
JESD-30 code	R-PDSO-G20
JESD-609 code	e3
length	6.5 mm
Humidity sensitivity level	1
Number of I/O lines	9
Number of ports	1
Number of terminals	20
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
Certification status	COMMERCIAL
Maximum seat height	1.1 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	2.7 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4.4 mm
uPs/uCs/peripheral integrated circuit type	PARALLEL IO PORT, GENERAL PURPOSE

DS4550E+ Preview

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Rev 0; 9/04

I

2

C and JTAG Nonvolatile 9-Bit I/O

Expander Plus Memory

General Description

The DS4550 is a 9-bit, nonvolatile (NV) I/O expander

with 64 bytes of NV user memory controlled by either

an I

2

C

TM

-compatible serial interface or an IEEE 1149.1

JTAG port. The DS4550 offers a digitally programmable

alternative to hardware jumpers and mechanical

switches that are being used to control digital logic

nodes. Each I/O pin is independently configurable. The

outputs are open drain with selectable pullups. Each

output has the ability to sink up to 16mA, and since the

device is NV, it powers up in the desired state allowing

it to control digital logic inputs immediately on power-

up without having to wait for the host CPU to initiate

control.

Features

♦

Programmable Replacement for Mechanical

Jumpers and Switches

♦

Nine NV Inputs/Outputs

♦

64-Byte NV User Memory (EEPROM)

♦

I

2

C-Compatible Serial Interface and JTAG

♦

Up to 8 Devices can be Multidropped on the Same

I

2

C Bus

♦

IEEE 1149.1 Boundary Scan Compliant

♦

Open-Drain Outputs with Configurable Pullups

♦

Outputs Capable of Sinking 16mA

♦

Low Power Consumption

♦

Wide Operating Voltage Range: 2.7V to 5.5V

♦

Operating Temperature Range: -40°C to +85°C

DS4550

Applications

RAM-Based FPGA Bank Switching for Multiple

Profiles

Selecting Between Boot Flash

Setting ASIC Configurations/Profiles

Servers

Network Storage

Routers

Telecom Equipment

PC Peripherals

Ordering Information

PART

DS4550E

TEMP RANGE

-40°C to +85°C

PIN-PACKAGE

20 TSSOP

Add “/T&R” for tape and reel orders.

Pin Configuration

TOP VIEW

V

CC

Typical Operating Circuit

I/O_0 1

I/O_1 2

I/O_2 3

I/O_3 4

I/O_4 5

A0 6

A1 7

TCK 8

TMS 9

V

CC

10

20 GND

19 I/O_8

18 I/O_7

17 I/O_6

16 I/O_5

4.7k

0.1µF

V

CC

A0

A1

A2

GND

SCL

SDA

TCK

TMS

TDI

TDO

DS4550

I/O_0

I/O_1

I/O_2

I/O_3

I/O_4

I/O_5

I/O_6

I/O_7

I/O_8

FPGA

CLOCK

GENERATOR

CPU SPEED

SELECT

DS4550

15 A2

14 TDO

13 TDI

12 SCL

11 SDA

I

2

C

INTERFACE

JTAG

INTERFACE

TSSOP

I

2

C is a trademark of Philips Corp. Purchase of I

2

C components from Maxim Integrated Products, Inc., or one of its sublicensed

Associated Companies, conveys a license under the Philips I

2

C Patent Rights to use these components in an I

2

C system, provided

that the system conforms to the I

2

C Standard Specification as defined by Philips.

______________________________________________

Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

I

2

C and JTAG Nonvolatile 9-Bit I/O

Expander Plus Memory

DS4550

ABSOLUTE MAXIMUM RATINGS

Voltage on V

CC

, SDA, and SCL Pins

Relative to Ground.............................................-0.5V to +6.0V

Voltage on A0, A1, A2, TCK, TMS, TDI, and I/O_n [n = 0 to 8]

Relative to Ground ...................................-0.5V to V

CC

+ 0.5V,

not to exceed +6.0V.

Operating Temperature Range ...........................-40°C to +85°C

EEPROM Programming Temperature Range .........0°C to +70°C

Storage Temperature Range .............................-55°C to +125°C

Soldering Temperature .....................See IPC/JEDEC J-STD-020

Specification

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

(T

A

= -40°C to +85°C)

PARAMETER

Supply Voltage

Input Logic 1

Input Logic 0

SYMBOL

V

CC

V

IH

V

IL

(Note 1)

CONDITIONS

MIN

+2.7

0.7 x

V

CC

-0.3

TYP

MAX

+5.5

V

CC

+

0.3

0.3 x

V

CC

UNITS

V

DC ELECTRICAL CHARACTERISTICS

(V

CC

= +2.7V to +5.5V, T

A

= -40°C to +85°C, unless otherwise noted.)

PARAMETER

Standby Current

Input Leakage

Input Current each I/O pin

Low-Level Output Voltage (SDA)

I/O Pins Low-Level Output

Voltage

Low-Level Output Voltage (TDO)

High-Level Output Voltage (TDO)

I/O Pin Pullup Resistors

TMS, TDI Pullup Resistors

I/O Capacitance

Power-On Reset Voltage

SYMBOL

I

STBY

I

L

I

I/O

V

OL SDA

V

OL I/O

V

OL TDO

V

OH TDO

R

PU

R

JPU

C

I/O

V

POR

(Note 3)

1.6

0.4 < V

I/O

< 0.9 x V

CC

3mA sink current

6mA sink current

16mA sink current

4mA sink current

1mA source current

2.4

4.0

7.5

5.5

10

7.5

12.5

10

(Note 2)

-1.0

CONDITIONS

MIN

TYP

2

MAX

10

+1.0

0.4

0.6

0.4

UNITS

µA

V

kΩ

pF

V

2

_____________________________________________________________________

I

2

C and JTAG Nonvolatile 9-Bit I/O

Expander Plus Memory

DS4550

AC ELECTRICAL CHARACTERISTICS-–I

2

C Interface (See

Figure

5)

(V

CC

= +2.7V to +5.5V, T

A

= -40°C to +85°C, unless otherwise noted. Timing referenced to V

IL(MAX)

and V

IH(MIN)

.)

PARAMETER

SCL Clock Frequency

Bus Free Time Between Stop and

Start Conditions

Hold Time (Repeated) Start

Condition

Low Period of SCL

High Period of SCL

Data Hold Time

Data Setup Time

Start Setup Time

SDA and SCL Rise Time

SDA and SCL Fall Time

Stop Setup Time

SDA and SCL Capacitive

Loading

EEPROM Write Time

SYMBOL

f

SCL

t

BUF

t

HD:STA

t

LOW

t

HIGH

t

HD:DAT

t

SU:DAT

t

SU:STA

t

R

t

F

t

SU:STO

C

B

t

WR

(Note 6)

I

2

C EEPROM write (Note 7)

10

(Note 6)

(Note 5)

(Note 4)

CONDITIONS

MIN

0

1.3

0.6

1.3

0.6

0

100

0.6

20 +

0.1C

B

20 +

0.1C

B

0.6

400

20

300

0.9

TYP

MAX

400

UNITS

kHz

µs

ns

µs

ns

µs

pF

ms

AC ELECTRICAL CHARACTERISTICSJTAG Interface (See

Figure

1)

(V

CC

= +2.7V to +5.5V, T

A

= -40°C to +85°C, unless otherwise noted.)

PARAMETER

TCK Clock Period

TCK Clock High/Low Time

TCK to TDI, TMS Setup Time

TCK to TDI, TMS Hold Time

TCK to TDO Delay

TCK to TDO High-Z Delay

EEPROM Write Time

SYMBOL

t

1

t

2

, t

3

t

4

t

5

t

6

t

7

t

WR

JTAG EEPROM write (Note 9)

10

(Note 8)

50

15

10

50

20

CONDITIONS

MIN

TYP

1000

500

MAX

UNITS

ns

ms

_____________________________________________________________________

3

I

2

C and JTAG Nonvolatile 9-Bit I/O

Expander Plus Memory

DS4550

NONVOLATILE MEMORY CHARACTERISTICS

(V

CC

= +2.7V to +5.5V, unless otherwise noted.)

PARAMETER

EEPROM Writes

SYMBOL

+70°C (Note 3)

CONDITIONS

MIN

50,000

TYP

MAX

UNITS

Note 1:

Note 2:

Note 3:

Note 4:

Note 5:

Note 6:

Note 7:

All voltages referenced to ground.

I

STBY

is specified with SDA = SCL = TMS = TDI = V

CC

, outputs floating, and inputs connected to V

CC

or GND.

Guaranteed by design.

Timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I

2

C standard mode timing.

After this period, the first clock pulse is generated.

C

B

total

capacitance of one bus line in picofarads.

EEPROM write time applies to all the EEPROM memory and SRAM-shadowed EEPROM memory when SEE = 0. The

EEPROM write time begins after a stop condition occurs.

Note 8:

TCK can be stopped either high or low.

Note 9:

EEPROM write begins immediately after the UPDATE-DR state that latches the data to be written. The EEPROM cannot be

accessed until the EEPROM write has completed. However, the remainder of the JTAG functionality is active and accessi-

ble during the EEPROM write.

t

1

t

2

t

3

TCK

t

4

t

5

TDI, TMS

t

6

t

7

TDO

Figure

1. JTAG Timing Diagram

4

_____________________________________________________________________

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