AT49BV640T-85TI datasheet, PDF

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AT49BV640T-85TI: DescriptionFlash, 4MX16, 85ns, PDSO48, 12 X 20 MM, PLASTIC, MO-142DD, TSOP1-48; Categorystorage storage; File Size194KB，30 Pages; ManufacturerAtmel (Microchip)

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AT49BV640T-85TI Overview

Flash, 4MX16, 85ns, PDSO48, 12 X 20 MM, PLASTIC, MO-142DD, TSOP1-48

AT49BV640T-85TI Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	TSOP1
package instruction	12 X 20 MM, PLASTIC, MO-142DD, TSOP1-48
Contacts	48
Reach Compliance Code	compliant
ECCN code	3A991.B.1.A
Maximum access time	85 ns
startup block	TOP
command user interface	YES
Universal Flash Interface	YES
Data polling	YES
JESD-30 code	R-PDSO-G48
JESD-609 code	e0
length	18.4 mm
memory density	67108864 bit
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of departments/size	8,127
Number of terminals	48
word count	4194304 words
character code	4000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	4MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP1
Encapsulate equivalent code	TSSOP48,.8,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
page size	4 words
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	3/3.3 V
Programming voltage	2.7 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Department size	4K,32K
Maximum standby current	0.00001 A
Maximum slew rate	0.05 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
switch bit	YES
type	NOR TYPE
width	12 mm

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Features

•

64-megabit (4M x 16) Flash Memory

•

2.7V - 3.6V Read/Write

•

High Performance

•

– Asynchronous Access Time – 70 ns

– Page Mode Read Time – 20 ns

Sector Erase Architecture

– Eight 4K Word Sectors with Individual Write Lockout

– 32K Word Main Sectors with Individual Write Lockout

Typical Sector Erase Time: 32K Word Sectors – 500 ms; 4K Word Sectors – 100 ms

Suspend/Resume Feature for Erase and Program

– Supports Reading and Programming Data from Any Sector by Suspending Erase

of a Different Sector

– Supports Reading Any Word by Suspending Programming of Any Other Word

Low-power Operation

– 30 mA Active

– 10 µA Standby

1.8V I/O Option Reduces Overall System Power

Data Polling and Toggle Bit for End of Program Detection

VPP Pin for Write Protection and Accelerated Program/Erase Operations

RESET Input for Device Initialization

TSOP or CBGA Package

Top or Bottom Boot Block Configuration Available

128-bit Protection Register

Common Flash Interface (CFI)

•

64-megabit

(4M x 16)

Page Mode

2.7-volt Flash

Memory

AT49BV640

AT49BV640T

Preliminary

Description

The AT49BV640(T) is a 2.7-volt 64-megabit Flash memory. The memory is divided

into multiple sectors for erase operations. The device can be read or reprogrammed

off a single 2.7V power supply, making it ideally suited for in-system programming.

The output voltage can be separately controlled down to 1.65V through the VCCQ

supply pin. This device can operate in the asynchronous or page read mode.

To increase the flexibility of the device, it contains an Erase Suspend and Program

Suspend feature. This feature will put the erase or program on hold for any amount of

time and let the user read data from or program data to any of the remaining sectors.

The end of a program or an erase cycle is detected by Data Polling or the toggle bit.

The VPP pin provides data protection and faster programming and erase times. When

the V

input is below 0.8V, the program and erase functions are inhibited. When V

is at 1.65V or above, normal program and erase operations can be performed. With

at 12.0V, the program and erase operations are accelerated.

With V

at 12V, a six-byte command (Enter Single Pulse Program Mode) to remove

the requirement of entering the three-byte program sequence is offered to further

improve programming time. After entering the six-byte code, only single pulses on the

write control lines are required for writing into the device. This mode (Single Pulse

Word Program) is exited by powering down the device, by taking the RESET pin to

GND or by a high-to-low transition on the V

input. Erase, Erase Suspend/Resume,

Program Suspend/Resume and Read Reset commands will not work while in this

mode; if entered they will result in data being programmed into the device. It is not rec-

ommended that the six-byte code reside in the software of the final product but only

exist in external programming code.

Rev. 3366B–FLASH–8/03

AT49BV640(T)

Device Operation

COMMAND SEQUENCES:

The device powers on in the read mode. Command

sequences are used to place the device in other operating modes such as program and

erase. After the completion of a program or an erase cycle, the device enters the read

mode. The command sequences are written by applying a low pulse on the WE input

with CE low and OE high or by applying a low-going pulse on the CE input with WE low

and OE high. The address is latched on the falling edge of the WE or CE pulse which-

ever occurs first. Valid data is latched on the rising edge of the WE or the CE pulse,

whichever occurs first. The addresses used in the command sequences are not affected

by entering the command sequences.

ASYNCHRONOUS READ:

The AT49BV640(T) is accessed like an EPROM. When CE

and OE are low and WE is high, the data stored at the memory location determined by

the address pins are asserted on the outputs. The outputs are put in the high impedance

state whenever CE or OE is high. This dual-line control gives designers flexibility in pre-

venting bus contention.

PAGE READ:

The page read operation of the device is controlled by CE and OE inputs.

The page size is four words. The first word access of the page read is the same as the

asynchronous read. The first word is read at an asynchronous speed of 80 ns. Once the

first word is read, toggling A0 and A1 will result in subsequent reads within the page

being output at a speed of 20 ns. The page read diagram is shown on page 20.

RESET:

A RESET input pin is provided to ease some system applications. When

RESET is at a logic high level, the device is in its standard operating mode. A low level

on the RESET pin halts the present device operation and puts the outputs of the device

in a high-impedance state. When a high level is reasserted on the RESET pin, the

device returns to read or standby mode, depending upon the state of the control pins.

ERASE:

Before a word can be reprogrammed it must be erased. The erased state of

the memory bits is a logical “1”. The entire memory can be erased by using the Chip

Erase command or individual sectors can be erased by using the Sector Erase

command.

CHIP ERASE:

Chip Erase is a six-bus cycle operation. The automatic erase begins on

the rising edge of the last WE pulse. Chip Erase does not alter the data of the protected

sectors. After the full chip erase the device will return back to the read mode. The hard-

ware reset during Chip Erase will stop the erase but the data will be of unknown state.

Any command during Chip Erase except Erase Suspend will be ignored.

SECTOR ERASE:

As an alternative to a full chip erase, the device is organized into

multiple sectors that can be individually erased. The Sector Erase command is a six-bus

cycle operation. The sector whose address is valid at the sixth falling edge of WE will be

erased provided the given sector has not been protected.

WORD PROGRAMMING:

The device is programmed on a word-by-word basis. Pro-

gramming is accomplished via the internal device command register and is a four-bus

cycle operation. The programming address and data are latched in the fourth cycle. The

device will automatically generate the required internal programming pulses. Please

note that a “0” cannot be programmed back to a “1”; only erase operations can convert

“0”s to “1”s.

FLEXIBLE SECTOR PROTECTION:

The AT49BV640(T) offers two sector protection

modes, the Softlock and the Hardlock. The Softlock mode is optimized as sector protec-

tion for sectors whose content changes frequently. The Hardlock protection mode is

recommended for sectors whose content changes infrequently. Once either of these two

modes is enabled, the contents of the selected sector is read-only and cannot be erased

3366B–FLASH–8/03

AT49BV640(T)

Table 2.

Sector Protection Status

I/O1

I/O0

Sector Protection Status

Sector Not Locked

Softlock Enabled

Hardlock Enabled

Both Hardlock and Softlock Enabled

PROGRAM/ERASE STATUS:

The device provides several bits to determine the status

of a program or erase operation: I/O2, I/O3, I/O5, I/O6, and I/O7. All other status bits are

don’t care. The Table 4 on page 25 and the following four sections describe the function

of these bits. To provide greater flexibility for system designers, the AT49BV640(T) con-

tains a programmable configuration register. The configuration register allows the user

to specify the status bit operation. The configuration register can be set to one of two dif-

ferent values, “00” or “01”. If the configuration register is set to “00”, the part will

automatically return to the read mode after a successful program or erase operation. If

the configuration register is set to a “01”, a Product ID Exit command must be given after

a successful program or erase operation before the part will return to the read mode. It

is important to note that whether the configuration register is set to a “00” or to a “01”,

any unsuccessful program or erase operation requires using the Product ID Exit com-

mand to return the device to read mode. The default value (after power-up) for the

configuration register is “00”. Using the four-bus cycle set configuration register com-

mand as shown in the Command Definition table on page 11, the value of the

configuration register can be changed. Voltages applied to the reset pin will not alter the

value of the configuration register. The value of the configuration register will affect the

operation of the I/O7 status bit as described below.

DATA POLLING:

The AT49BV640(T) features Data Polling to indicate the end of a pro-

gram cycle. If the status configuration register is set to a “00”, during a program cycle an

attempted read of the last word loaded will result in the complement of the loaded data

on I/O7. Once the program cycle has been completed, true data is valid on all outputs

and the next cycle may begin. During a chip erase or sector erase operation, an attempt

to read the device will give a “0” on I/O7. Once the program or erase cycle has com-

pleted, true data will be read from the device. Data Polling may begin at any time during

the program cycle. Please see Table 3 on page 10 for more details.

If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while

the device is actively programming or erasing data. I/O7 will go high when the device

has completed a program or erase operation. Once I/O7 has gone high, status informa-

tion on the other pins can be checked.

The Data Polling status bit must be used in conjunction with the erase/program and V

status bit as shown in the algorithm in Figures 2 and 3.

TOGGLE BIT:

In addition to Data Polling, the AT49BV640(T) provides another method

for determining the end of a program or erase cycle. During a program or erase opera-

tion, successive attempts to read data from the memory will result in I/O6 toggling

between one and zero. Once the program cycle has completed, I/O6 will stop toggling

and valid data will be read. Examining the toggle bit may begin at any time during a pro-

gram cycle. Please see Table 3 on page 10 for more details.

The toggle bit status bit should be used in conjunction with the erase/program and V

status bit as shown in the algorithm in Figures 4 and 5 on page 9.

3366B–FLASH–8/03

AT49BV640T-85TI Related Products

	AT49BV640T-85TI	AT49BV640T-85CI	AT49BV640T-70TI	AT49BV640-85TI	AT49BV640-85CI	AT49BV640T-70CI	AT49BV640-70CI	AT49BV640-70TI
Description	Flash, 4MX16, 85ns, PDSO48, 12 X 20 MM, PLASTIC, MO-142DD, TSOP1-48	Flash, 4MX16, 85ns, PBGA48, 8 X 11 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, CBGA-48	Flash, 4MX16, 70ns, PDSO48, 12 X 20 MM, PLASTIC, MO-142DD, TSOP1-48	Flash, 4MX16, 85ns, PDSO48, 12 X 20 MM, PLASTIC, MO-142DD, TSOP1-48	Flash, 4MX16, 85ns, PBGA48, 8 X 11 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, CBGA-48	Flash, 4MX16, 70ns, PBGA48, 8 X 11 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, CBGA-48	Flash, 4MX16, 70ns, PBGA48, 8 X 11 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, CBGA-48	Flash, 4MX16, 70ns, PDSO48, 12 X 20 MM, PLASTIC, MO-142DD, TSOP1-48
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Parts packaging code	TSOP1	BGA	TSOP1	TSOP1	BGA	BGA	BGA	TSOP1
package instruction	12 X 20 MM, PLASTIC, MO-142DD, TSOP1-48	8 X 11 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, CBGA-48	12 X 20 MM, PLASTIC, MO-142DD, TSOP1-48	12 X 20 MM, PLASTIC, MO-142DD, TSOP1-48	8 X 11 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, CBGA-48	TFBGA, BGA48,6X8,32	TFBGA, BGA48,6X8,32	12 X 20 MM, PLASTIC, MO-142DD, TSOP1-48
Contacts	48	48	48	48	48	48	48	48
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant
ECCN code	3A991.B.1.A	3A991.B.1.A	3A991.B.1.A	3A991.B.1.A	3A991.B.1.A	3A991.B.1.A	3A991.B.1.A	3A991.B.1.A
Maximum access time	85 ns	85 ns	70 ns	85 ns	85 ns	70 ns	70 ns	70 ns
startup block	TOP	TOP	TOP	BOTTOM	BOTTOM	TOP	BOTTOM	BOTTOM
command user interface	YES	YES	YES	YES	YES	YES	YES	YES
Universal Flash Interface	YES	YES	YES	YES	YES	YES	YES	YES
Data polling	YES	YES	YES	YES	YES	YES	YES	YES
JESD-30 code	R-PDSO-G48	R-PBGA-B48	R-PDSO-G48	R-PDSO-G48	R-PBGA-B48	R-PBGA-B48	R-PBGA-B48	R-PDSO-G48
JESD-609 code	e0	e0	e0	e0	e0	e0	e0	e0
length	18.4 mm	11 mm	18.4 mm	18.4 mm	11 mm	11 mm	11 mm	18.4 mm
memory density	67108864 bit	67108864 bit	67108864 bit	67108864 bit	67108864 bit	67108864 bit	67108864 bit	67108864 bit
Memory IC Type	FLASH	FLASH	FLASH	FLASH	FLASH	FLASH	FLASH	FLASH
memory width	16	16	16	16	16	16	16	16
Number of functions	1	1	1	1	1	1	1	1
Number of departments/size	8,127	8,127	8,127	8,127	8,127	8,127	8,127	8,127
Number of terminals	48	48	48	48	48	48	48	48
word count	4194304 words	4194304 words	4194304 words	4194304 words	4194304 words	4194304 words	4194304 words	4194304 words
character code	4000000	4000000	4000000	4000000	4000000	4000000	4000000	4000000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
organize	4MX16	4MX16	4MX16	4MX16	4MX16	4MX16	4MX16	4MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP1	TFBGA	TSOP1	TSOP1	TFBGA	TFBGA	TFBGA	TSOP1
Encapsulate equivalent code	TSSOP48,.8,20	BGA48,6X8,32	TSSOP48,.8,20	TSSOP48,.8,20	BGA48,6X8,32	BGA48,6X8,32	BGA48,6X8,32	TSSOP48,.8,20
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	GRID ARRAY, THIN PROFILE, FINE PITCH	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	SMALL OUTLINE, THIN PROFILE
page size	4 words	4 words	4 words	4 words	4 words	4 words	4 words	4 words
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	240	240	240	240	240	240	240	240
power supply	3/3.3 V	3/3.3 V	3/3.3 V	3/3.3 V	3/3.3 V	3/3.3 V	3/3.3 V	3/3.3 V
Programming voltage	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
Department size	4K,32K	4K,32K	4K,32K	4K,32K	4K,32K	4K,32K	4K,32K	4K,32K
Maximum standby current	0.00001 A	0.00001 A	0.00001 A	0.00001 A	0.00001 A	0.00001 A	0.00001 A	0.00001 A
Maximum slew rate	0.05 mA	0.05 mA	0.05 mA	0.05 mA	0.05 mA	0.05 mA	0.05 mA	0.05 mA
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
Nominal supply voltage (Vsup)	3 V	3 V	3 V	3 V	3 V	3 V	3 V	3 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	BALL	GULL WING	GULL WING	BALL	BALL	BALL	GULL WING
Terminal pitch	0.5 mm	0.8 mm	0.5 mm	0.5 mm	0.8 mm	0.8 mm	0.8 mm	0.5 mm
Terminal location	DUAL	BOTTOM	DUAL	DUAL	BOTTOM	BOTTOM	BOTTOM	DUAL
Maximum time at peak reflow temperature	30	30	30	30	30	30	30	30
switch bit	YES	YES	YES	YES	YES	YES	YES	YES
type	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE
width	12 mm	8 mm	12 mm	12 mm	8 mm	8 mm	8 mm	12 mm
Maker	Atmel (Microchip)	Atmel (Microchip)	-	-	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)	Atmel (Microchip)

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