Features
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64-megabit (4M x 16) Flash Memory
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2.7V - 3.6V Read/Write
•
High Performance
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– Asynchronous Access Time – 70 ns
– Page Mode Read Time – 20 ns
Sector Erase Architecture
– Eight 4K Word Sectors with Individual Write Lockout
– 32K Word Main Sectors with Individual Write Lockout
Typical Sector Erase Time: 32K Word Sectors – 500 ms; 4K Word Sectors – 100 ms
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
– 30 mA Active
– 10 µA Standby
1.8V I/O Option Reduces Overall System Power
Data Polling and Toggle Bit for End of Program Detection
VPP Pin for Write Protection and Accelerated Program/Erase Operations
RESET Input for Device Initialization
TSOP or CBGA Package
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
Common Flash Interface (CFI)
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64-megabit
(4M x 16)
Page Mode
2.7-volt Flash
Memory
AT49BV640
AT49BV640T
Preliminary
Description
The AT49BV640(T) is a 2.7-volt 64-megabit Flash memory. The memory is divided
into multiple sectors for erase operations. The device can be read or reprogrammed
off a single 2.7V power supply, making it ideally suited for in-system programming.
The output voltage can be separately controlled down to 1.65V through the VCCQ
supply pin. This device can operate in the asynchronous or page read mode.
To increase the flexibility of the device, it contains an Erase Suspend and Program
Suspend feature. This feature will put the erase or program on hold for any amount of
time and let the user read data from or program data to any of the remaining sectors.
The end of a program or an erase cycle is detected by Data Polling or the toggle bit.
The VPP pin provides data protection and faster programming and erase times. When
the V
PP
input is below 0.8V, the program and erase functions are inhibited. When V
PP
is at 1.65V or above, normal program and erase operations can be performed. With
V
PP
at 12.0V, the program and erase operations are accelerated.
With V
PP
at 12V, a six-byte command (Enter Single Pulse Program Mode) to remove
the requirement of entering the three-byte program sequence is offered to further
improve programming time. After entering the six-byte code, only single pulses on the
write control lines are required for writing into the device. This mode (Single Pulse
Word Program) is exited by powering down the device, by taking the RESET pin to
GND or by a high-to-low transition on the V
PP
input. Erase, Erase Suspend/Resume,
Program Suspend/Resume and Read Reset commands will not work while in this
mode; if entered they will result in data being programmed into the device. It is not rec-
ommended that the six-byte code reside in the software of the final product but only
exist in external programming code.
Rev. 3366B–FLASH–8/03
1
Pin Configurations
Pin Name
I/O0 - I/O15
A0 - A21
CE
OE
WE
RESET
WP
VPP
VCCQ
Pin Function
Data Inputs/Outputs
Addresses
Chip Enable
Output Enable
Write Enable
Reset
Write Protect
Write Protection and Power Supply for
Accelerated Program/Erase Operations
Output Power Supply
A15
A14
A13
A12
A11
A10
A9
A8
A21
A20
WE
RESET
VPP
WP
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AT49BV640(T)
TSOP Top View
Type 1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
VCCQ
GND
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
AT49BV640(T)
CBGA Top View
1
A
A13
2
3
4
5
6
7
8
A11
A10
A12
I/O14
A8
WE
A9
I/O5
I/O6
I/O13
VPP
RST
A21
I/O11
I/O12
I/O4
WP
A18
A20
I/O2
I/O3
VCC
A19
A17
A6
I/O8
I/O9
I/O10
A7
A5
A3
CE
I/O0
I/O1
A4
A2
A1
A0
GND
OE
B
A14
C
A15
D
A16
E
VCCQ I/O15
F
GND
I/O7
2
AT49BV640(T)
3366B–FLASH–8/03
AT49BV640(T)
Device Operation
COMMAND SEQUENCES:
The device powers on in the read mode. Command
sequences are used to place the device in other operating modes such as program and
erase. After the completion of a program or an erase cycle, the device enters the read
mode. The command sequences are written by applying a low pulse on the WE input
with CE low and OE high or by applying a low-going pulse on the CE input with WE low
and OE high. The address is latched on the falling edge of the WE or CE pulse which-
ever occurs first. Valid data is latched on the rising edge of the WE or the CE pulse,
whichever occurs first. The addresses used in the command sequences are not affected
by entering the command sequences.
ASYNCHRONOUS READ:
The AT49BV640(T) is accessed like an EPROM. When CE
and OE are low and WE is high, the data stored at the memory location determined by
the address pins are asserted on the outputs. The outputs are put in the high impedance
state whenever CE or OE is high. This dual-line control gives designers flexibility in pre-
venting bus contention.
PAGE READ:
The page read operation of the device is controlled by CE and OE inputs.
The page size is four words. The first word access of the page read is the same as the
asynchronous read. The first word is read at an asynchronous speed of 80 ns. Once the
first word is read, toggling A0 and A1 will result in subsequent reads within the page
being output at a speed of 20 ns. The page read diagram is shown on page 20.
RESET:
A RESET input pin is provided to ease some system applications. When
RESET is at a logic high level, the device is in its standard operating mode. A low level
on the RESET pin halts the present device operation and puts the outputs of the device
in a high-impedance state. When a high level is reasserted on the RESET pin, the
device returns to read or standby mode, depending upon the state of the control pins.
ERASE:
Before a word can be reprogrammed it must be erased. The erased state of
the memory bits is a logical “1”. The entire memory can be erased by using the Chip
Erase command or individual sectors can be erased by using the Sector Erase
command.
CHIP ERASE:
Chip Erase is a six-bus cycle operation. The automatic erase begins on
the rising edge of the last WE pulse. Chip Erase does not alter the data of the protected
sectors. After the full chip erase the device will return back to the read mode. The hard-
ware reset during Chip Erase will stop the erase but the data will be of unknown state.
Any command during Chip Erase except Erase Suspend will be ignored.
SECTOR ERASE:
As an alternative to a full chip erase, the device is organized into
multiple sectors that can be individually erased. The Sector Erase command is a six-bus
cycle operation. The sector whose address is valid at the sixth falling edge of WE will be
erased provided the given sector has not been protected.
WORD PROGRAMMING:
The device is programmed on a word-by-word basis. Pro-
gramming is accomplished via the internal device command register and is a four-bus
cycle operation. The programming address and data are latched in the fourth cycle. The
device will automatically generate the required internal programming pulses. Please
note that a “0” cannot be programmed back to a “1”; only erase operations can convert
“0”s to “1”s.
FLEXIBLE SECTOR PROTECTION:
The AT49BV640(T) offers two sector protection
modes, the Softlock and the Hardlock. The Softlock mode is optimized as sector protec-
tion for sectors whose content changes frequently. The Hardlock protection mode is
recommended for sectors whose content changes infrequently. Once either of these two
modes is enabled, the contents of the selected sector is read-only and cannot be erased
3
3366B–FLASH–8/03
or programmed. Each sector can be independently programmed for either the Softlock
or Hardlock sector protection mode. At power-up and reset, all sectors have their Soft-
lock protection mode enabled.
SOFTLOCK AND UNLOCK:
The Softlock protection mode can be disabled by issuing a
two-bus cycle Unlock command to the selected sector. Once a sector is unlocked, its
contents can be erased or programmed. To enable the Softlock protection mode, a six-
bus cycle Softlock command must be issued to the selected sector.
HARDLOCK AND WRITE PROTECT (WP):
The Hardlock sector protection mode oper-
ates in conjunction with the Write Protection (WP) pin. The Hardlock sector protection
mode can be enabled by issuing a six-bus cycle Hardlock software command to the
selected sector. The state of the Write Protect pin affects whether the Hardlock protec-
tion mode can be overridden.
• When the WP pin is low and the Hardlock protection mode is enabled, the sector
cannot be unlocked and the contents of the sector is read-only.
• When the WP pin is high, the Hardlock protection mode is overridden and the sector
can be unlocked via the Unlock command.
To disable the Hardlock sector protection mode, the chip must be either reset or power
cycled.
Table 1.
Hardlock and Softlock Protection Configurations in Conjunction with WP
Hard
lock
0
0
Soft
lock
0
1
Erase/
Prog
Allowed?
Yes
No
V
PP
V
CC
/5V
V
CC
/5V
WP
0
0
Comments
No sector is locked
Sector is Softlocked. The
Unlock command can unlock
the sector.
Hardlock protection mode is
enabled. The sector cannot
be unlocked.
No sector is locked.
Sector is Softlocked. The
Unlock command can unlock
the sector.
Hardlock protection mode is
overridden and the sector is
not locked.
Hardlock protection mode is
overridden and the sector
can be unlocked via the
Unlock command.
Erase and Program
Operations cannot be
performed.
V
CC
/5V
0
1
1
No
V
CC
/5V
V
CC
/5V
1
1
0
0
0
1
Yes
No
V
CC
/5V
1
1
0
Yes
V
CC
/5V
1
1
1
No
V
IL
x
x
x
No
SECTOR PROTECTION DETECTION:
A software method is available to determine if
the sector protection Softlock or Hardlock features are enabled. When the device is in
the software product identification mode (see Software Product Identification Entry and
Exit sections) a read from the I/O0 and I/O1 at address location 00002H within a sector
will show if the sector is unlocked, softlocked, or hardlocked.
4
AT49BV640(T)
3366B–FLASH–8/03
AT49BV640(T)
Table 2.
Sector Protection Status
I/O1
0
0
1
1
I/O0
0
1
0
1
Sector Protection Status
Sector Not Locked
Softlock Enabled
Hardlock Enabled
Both Hardlock and Softlock Enabled
PROGRAM/ERASE STATUS:
The device provides several bits to determine the status
of a program or erase operation: I/O2, I/O3, I/O5, I/O6, and I/O7. All other status bits are
don’t care. The Table 4 on page 25 and the following four sections describe the function
of these bits. To provide greater flexibility for system designers, the AT49BV640(T) con-
tains a programmable configuration register. The configuration register allows the user
to specify the status bit operation. The configuration register can be set to one of two dif-
ferent values, “00” or “01”. If the configuration register is set to “00”, the part will
automatically return to the read mode after a successful program or erase operation. If
the configuration register is set to a “01”, a Product ID Exit command must be given after
a successful program or erase operation before the part will return to the read mode. It
is important to note that whether the configuration register is set to a “00” or to a “01”,
any unsuccessful program or erase operation requires using the Product ID Exit com-
mand to return the device to read mode. The default value (after power-up) for the
configuration register is “00”. Using the four-bus cycle set configuration register com-
mand as shown in the Command Definition table on page 11, the value of the
configuration register can be changed. Voltages applied to the reset pin will not alter the
value of the configuration register. The value of the configuration register will affect the
operation of the I/O7 status bit as described below.
DATA POLLING:
The AT49BV640(T) features Data Polling to indicate the end of a pro-
gram cycle. If the status configuration register is set to a “00”, during a program cycle an
attempted read of the last word loaded will result in the complement of the loaded data
on I/O7. Once the program cycle has been completed, true data is valid on all outputs
and the next cycle may begin. During a chip erase or sector erase operation, an attempt
to read the device will give a “0” on I/O7. Once the program or erase cycle has com-
pleted, true data will be read from the device. Data Polling may begin at any time during
the program cycle. Please see Table 3 on page 10 for more details.
If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while
the device is actively programming or erasing data. I/O7 will go high when the device
has completed a program or erase operation. Once I/O7 has gone high, status informa-
tion on the other pins can be checked.
The Data Polling status bit must be used in conjunction with the erase/program and V
PP
status bit as shown in the algorithm in Figures 2 and 3.
TOGGLE BIT:
In addition to Data Polling, the AT49BV640(T) provides another method
for determining the end of a program or erase cycle. During a program or erase opera-
tion, successive attempts to read data from the memory will result in I/O6 toggling
between one and zero. Once the program cycle has completed, I/O6 will stop toggling
and valid data will be read. Examining the toggle bit may begin at any time during a pro-
gram cycle. Please see Table 3 on page 10 for more details.
The toggle bit status bit should be used in conjunction with the erase/program and V
PP
status bit as shown in the algorithm in Figures 4 and 5 on page 9.
5
3366B–FLASH–8/03
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