September 1996
Revision 1.0
DATA SHEET
EDC4UV644(2/4)-(60/70)(J/T)G-S
32MByte (4M x 64) CMOS EDO DRAM Module - 3.3V
General Description
The EDC4UV644(2/4)-(60/70)(J/T)G-S is a high performance, EDO (Extended Data Out) 32-megabyte dynamic RAM module
organized as 4M words by 64 bits, in a 168-pins, dual-in-line (DIMM) memory modules.
The module utilizes sixteen, Fujitsu MB81V1(7/6)405A-(60/70) (PJ/FN) CMOS 4Mx4 EDO dynamic RAMs in a surface mount
package on an epoxy laminate substrate. Each device is accompanied by a decoupling capacitor for improved noise immunity.
Control lines provided are such that byte control is possible. Serial PD on the module is provided by using 128 byte serial EEPROM.
Features
• High Density: 32MByte
• Fast Access Time of 60/70 ns (max.)
• Low Power:
6.3/5.5 W (max.
5.2/4.6 W (max.)
115mW (max.)
58mW (max.)
- Active (60/70 ns) : 2KR
- Active (60/70 ns) : 4KR
- Standby (LVTTL)
- Standby (CMOS)
• LVTTL-compatible inputs and outputs
• Separate power and ground planes to improve noise immunity
• Single power supply of 3.3V±0.3V
• Height: 1.00 inch
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on any pin relative to V
SS
Power Dissipation
Operating Temperature
Storage Temperate
Short Circuit Output Current
Symbol
V
T
P
T
T
opr
T
stg
I
OS
Ratings
-0.5 to +4.6
16
0 to +70
-55 to +125
50
Unit
V
W
°
C
°
C
mA
RECOMMENDED DC OPERATING CONDITIONS
(T
A
= 0 to +70
°C)
Symbol
V
CC
V
SS
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High voltage
Input Low voltage
Min
3.0
0
2.0
-0.3
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+0.3
0.8
Unit
V
V
V
V
Fujitsu Microelectronics, Inc.
1
September 1996
Revision 1.0
EDC4UV644(2/4)-(60/70)(J/T)G-S
Functional Diagram
CAS7*
CAS6*
CAS5*
CAS4*
CAS3*
CAS2*
CAS1*
CAS0*
RAS0*
WE0*
OE0*
DQ0~DQ15
4Mx16
Block
4Mx16
Block
RAS2*
WE2*
OE2*
DQ16~DQ31
DQ62~DQ47
DQ48~DQ63
4Mx16
Block
4Mx16
Block
DQ0~DQ63
SERIAL PD EEPROM
SCL
SDA
SA0
SA1
SA2
A0
A1
A2
V
CC
V
SS
Decoupling capacitors
to all devices
(All specifications of the device are subject to change without notice.)
Notes:
1.
2.
3.
“*” signifies active low signal.
Addresses A0 ~ A10 are connected to all DRAMs.
Each 4Mx16 block is comprised of four 4Mx4 EDO DRAMs.
2
Fujitsu Microelectronics, Inc.
September 1996
Revision 1.0
EDC4UV644(2/4)-(60/70)(J/T)G-S
Pin Name
A0~A10
DQ0~DQ63
WE0*, WE2*
RAS0*, RAS2*
SDA
OE0*, OE2*
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Addresses
Data Inputs/Outputs
Write Enable
Row Address Strobes
Serial Data Input/Output
Output Enable
Pin No.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Pin Designation
V
SS
OE2*
RAS2*
CAS2*
CAS3*
WE2*
V
CC
NC
NC
NC
NC
V
SS
DQ16
DQ17
DQ18
DQ19
V
CC
DQ20
NC
NC
NC
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
CC
DQ28
DQ29
DQ30
DQ31
V
SS
NC
NC
NC
SDA
SCL
V
CC
Pin No.
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
CAS0*~CAS7*
SA0~SA2
SCL
V
CC
V
SS
NC
Pin Designation
V
SS
DQ32
DQ33
DQ34
DQ35
V
CC
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
CC
DQ46
DQ47
NC
NC
V
SS
NC
NC
V
CC
NC
CAS4*
CAS5*
NC
NC
V
SS
A1
A3
A5
A7
A9
NC
NC
V
CC
NC
NC
Column Address Strobes
Decode Inputs
Serial Clock
Power Supply
Ground
No Connection
Pin No.
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Pin Designation
V
SS
NC
NC
CAS6*
CAS7*
NC
V
CC
NC
NC
NC
NC
V
SS
DQ48
DQ49
DQ50
DQ51
V
CC
DQ52
NC
NC
NC
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
CC
DQ60
DQ61
DQ62
DQ63
V
SS
NC
NC
SA0
SA1
SA2
V
CC
Pin Designation
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
NC
NC
V
SS
NC
NC
V
CC
WE0*
CAS0*
CAS1*
RAS0*
OE0*
V
SS
A0
A2
A4
A6
A8
A10
NC
V
CC
V
CC
NC
Fujitsu Microelectronics, Inc.
3
September 1996
Revision 1.0
EDC4UV644(2/4)-(60/70)(J/T)G-S
DC CHARACTERISTICS
(V
CC
= 3.3V±0.3V, V
SS
= 0V, T
A
= 0 to +70
°C)
60
Parameter
Symbol
Test Condition
Min.
Operating Current
I
CC1
RAS*, CAS* cycling; t
RC
= min.
LVTTL Interface
RAS*, CAS*
≥
V
IH
D
out
= HIgh-Z
CMOS Interface
RAS*, CAS*
≥
V
cc
- 0.2V
D
out
= HIgh-Z
CAS*
≥
V
IH
; RAS*, Address
cycling @ t
RC
= min.
RAS*, CAS* cycling @
t
RC
= min.
RAS*
≤
V
IL
; CAS*, Address
cycling @ t
PC
= min.
0V
≤
V
in
≤
V
CC
+ 0.3V
0V
≤
V
out
≤
V
CC
D
out
= Disable
High I
out
= -2mA
Low I
out
= 2 mA
2KR
4KR
2KR
4KR
-
-160
-10
2.4
0
-
2KR
4KR
-
-
Max.
1760
1280
32
-
Min.
-
Max.
1520
mA
1120
32
mA
1, 2
70
Unit
Note
Standby current
I
CC2
-
-
16
1760
1280
1760
1280
1440
160
10
-
0.4
-
-
16
1520
mA
RAS* -only Refresh
Current
CAS*-before-RAS*
Refresh Current
Hyper Page Mode
Current
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Notes:
1.
2.
3.
I
CC3
mA
1120
-
1520
mA
1120
-
-160
-10
2.4
0
1280
160
10
-
0.4
mA
2
I
CC4
2
I
CC5
I
LI
I
LO
V
OH
V
OL
1, 3
µ
A
µ
A
V
V
Values depend on output load condition when the device is selected. Maximum Values are specified at the output open condition.
Address can be changed once or less while RAS* = V
IL
.
Address can be changed once or less while CAS* = V
IH
.
CAPACITANCE
(TA =+25°C, V
CC
= 3.3V±0.3V)
Parameter
Input Capacitance (Address)
Input Capacitance (RAS*, OE*, WE*)
Input Capacitance (CAS0*~CAS7*)
Input/Output Capacitance (DQ0~DQ63)
Notes:
1.
2.
Symbol
C
I1
C
I2
C
I3
C
I/O
Max.
85
45
15
12
Unit
pF
pF
pF
pF
Note
1
1
1
1, 2
Capacitance is measured with Boonton Meter or effective capacitance method.
CAS* - V
IH
to disable D
out
.
4
Fujitsu Microelectronics, Inc.
September 1996
Revision 1.0
EDC4UV644(2/4)-(60/70)(J/T)G-S
AC CHARACTERISTICS
(TA = 0 to +70°C, V
CC
= 3.3V±0.3V, V
SS
= 0V)
Parameter
Random read/write cycle time
Access time from RAS*
Access time from CAS*
Access time from column address
Transition time (rise and fall)
RAS* precharge time
RAS* pulse width
RAS* hold time
CAS* hold time
CAS* pulse width
RAS* to CAS* delay time
RAS* to column address delay time
CAS* to RAS* precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS* lead time
Read command set-up time
Read command hold time to CAS*
Read command hold time to RAS*
Write command hold time
Write command pulse width
Write command to RAS* lead time
Write command to CAS* lead time
Data-in set-up time
Data-in hold time
Refresh period
Write command set-up time
CAS* set-up time (CBR refresh)
CAS* hold time (CBR refresh)
RAS* precharge to CAS* hold time
Access time from CAS* precharge
Hyper page mode cycle time
CAS* precharge time (Hyper page)
RAS* pulse width (Hyper page)
2KR
4KR
Symbol
t
RC
t
RAC
t
CAC
t
AA
t
T
t
RP
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
t
RCS
t
RCH
t
RRH
t
WCH
t
WP
t
RWL
t
CWL
t
DS
t
DH
t
REF
t
WCS
t
CSR
t
CHR
t
RPC
t
CPA
t
HPC
t
CP
t
RASP
60
Min
110
-
-
-
2
40
60
15
45
10
20
15
5
0
10
0
10
30
5
0
0
10
10
15
10
0
10
-
-
0
10
10
5
-
25
10
60
Max
-
60
15
30
50
-
10000
-
-
10000
45
30
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
32
64
-
-
-
-
35
-
-
100000
Min
130
-
-
-
2
50
70
20
50
15
20
15
5
0
10
0
15
35
5
0
0
15
15
20
15
0
15
-
-
0
10
15
5
-
30
10
70
70
Max
-
70
20
35
50
-
10000
-
-
10000
50
35
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
32
64
-
-
-
-
40
-
-
100000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
12
3, 11
7
1
1
9
9
8
4
10
3, 4
3, 4, 5
3, 10
2
Notes
Fujitsu Microelectronics, Inc.
5
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