AD9252_15 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > AD9252_15

Preview

AD9252_15: DescriptionOctal, 14-Bit, 50 MSPS, Serial LVDS, 1.8 V ADC; File Size2MB，52 Pages; ManufacturerADI; Websitehttps://www.analog.com

Download Datasheet View All

AD9252_15 Overview

Octal, 14-Bit, 50 MSPS, Serial LVDS, 1.8 V ADC

Preview

Download Datasheet

View All

Data Sheet

FEATURES

8 analog-to-digital converters (ADCs) integrated into 1 package

93.5 mW ADC power per channel at 50 MSPS

SNR = 73 dB (to Nyquist)

ENOB = 12 bits

SFDR = 84 dBc (to Nyquist)

Excellent linearity

DNL = ±0.4 LSB (typical); INL = ±1.5 LSB (typical)

Serial LVDS (ANSI-644, default)

Low power, reduced signal option (similar to IEEE 1596.3)

Data and frame clock outputs

325 MHz, full-power analog bandwidth

2 V p-p input voltage range

1.8 V supply operation

Serial port control

Full-chip and individual-channel power-down modes

Flexible bit orientation

Built-in and custom digital test pattern generation

Programmable clock and data alignment

Programmable output resolution

Standby mode

AVDD

Octal, 14-Bit, 50 MSPS,

Serial LVDS, 1.8 V ADC

AD9252

FUNCTIONAL BLOCK DIAGRAM

PDWN

DRVDD

DRGND

AD9252

VIN + A

VIN – A

VIN + B

VIN – B

VIN + C

VIN – C

VIN + D

VIN – D

VIN + E

VIN – E

VIN + F

VIN – F

VIN + G

VIN – G

VIN + H

VIN – H

VREF

SENSE

0.5V

REFT

REFB

REF

SELECT

SERIAL PORT

INTERFACE

ADC

SERIAL

LVDS

ADC

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

D+A

D–A

D+B

D–B

D+C

D–C

D+D

D–D

D+E

D–E

D+F

D–F

D+G

D–G

D+H

D–H

APPLICATIONS

Medical imaging and nondestructive ultrasound

Portable ultrasound and digital beam-forming systems

Quadrature radio receivers

Diversity radio receivers

Tape drives

Optical networking

Test equipment

FCO+

DATA RATE

MULTIPLIER

FCO–

DCO+

DCO–

06296-001

RBIAS

AGND CSB

SDIO/

ODM

SCLK/

DTP

CLK+

CLK–

Figure 1.

GENERAL DESCRIPTION

The AD9252 is an octal, 14-bit, 50 MSPS ADC with an on-chip

sample-and-hold circuit designed for low cost, low power, small size,

and ease of use. Operating at a conversion rate of up to 50 MSPS,

it is optimized for outstanding dynamic performance and low

power in applications where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/

CMOS-/LVDS-compatible sample rate clock for full performance

operation. No external reference or driver components are

required for many applications.

The ADC automatically multiplies the sample rate clock for

the appropriate LVDS serial data rate. A data clock (DCO)

for capturing data on the output and a frame clock (FCO) for

signaling a new output byte are provided. Individual channel

power-down is supported and typically consumes less than

2 mW when all channels are disabled.

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

The ADC contains several features designed to maximize

flexibility and minimize system cost, such as programmable

clock and data alignment and programmable digital test pattern

generation. The available digital test patterns include built-in

deterministic and pseudorandom patterns, along with custom user-

defined test patterns entered via the serial port interface (SPI).

The AD9252 is available in an RoHS compliant, 64-lead LFCSP. It is

specified over the industrial temperature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

Small Footprint. Eight ADCs are contained in a small package.

Low Power of 93.5 mW per Channel at 50 MSPS.

Ease of Use. A data clock output (DCO) operates up to

350 MHz and supports double data rate (DDR) operation.

User Flexibility. SPI control offers a wide range of flexible

features to meet specific system requirements.

Pin-Compatible Family. This includes the

AD9212

(10-bit)

and

AD9222

(12-bit).

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD9252

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications .............................................................. 6

Timing Diagrams.......................................................................... 7

Absolute Maximum Ratings ............................................................ 9

Thermal Impedance ..................................................................... 9

ESD Caution .................................................................................. 9

Pin Configuration and Function Descriptions ........................... 10

Equivalent Circuits ......................................................................... 12

Typical Performance Characteristics ........................................... 14

Theory of Operation ...................................................................... 17

Analog Input Considerations.................................................... 17

Data Sheet

Clock Input Considerations ...................................................... 19

Serial Port Interface (SPI) .............................................................. 27

Hardware Interface ..................................................................... 27

Memory Map .................................................................................. 29

Reading the Memory Map Table .............................................. 29

Reserved Locations .................................................................... 29

Default Values ............................................................................. 29

Logic Levels ................................................................................. 29

Applications Information .............................................................. 32

Design Guidelines ...................................................................... 32

Evaluation Board ............................................................................ 33

Power Supplies ............................................................................ 33

Input Signals................................................................................ 33

Output Signals ............................................................................ 33

Default Operation and Jumper Selection Settings ................. 34

Alternative Analog Input Drive Configuration...................... 35

Outline Dimensions ....................................................................... 52

Ordering Guide .......................................................................... 52

REVISION HISTORY

12/11—Rev. D to Rev. E

Changes to Output Signals Section and Figure 58 ..................... 33

Change to Default Operation and Jumper Selection Settings

Section .............................................................................................. 34

Added Endnote 2 in Ordering Guide .......................................... 52

4/10—Rev. C to Rev. D

Changes to Address 16 in Table 16............................................... 31

Updated Outline Dimensions ....................................................... 52

Changes to Ordering Guide .......................................................... 52

12/09—Rev. B to Rev. C

Updated Outline Dimensions ....................................................... 52

Changes to Ordering Guide .......................................................... 52

7/09—Rev. A to Rev. B

Changes to Figure 5 ........................................................................ 10

Changes to Figure 38 and Figure 39............................................. 18

Changes to Figure 51 and Figure 52............................................. 25

Updated Outline Dimensions ....................................................... 52

12/07—Rev. 0 to Rev. A

Changes to Features.......................................................................... 1

Changes to Crosstalk Parameter..................................................... 3

Changes to Figure 2 to Figure 4 ...................................................... 7

Changes to Table 9 Endnote .......................................................... 23

Changes to Digital Outputs and Timing Section ....................... 24

Added Table 10 ............................................................................... 24

Changes to Table 11 and Table 12 ................................................ 24

Changes to RBIAS Pin Section ..................................................... 25

Deleted Figure 51 to Figure 52...................................................... 25

Moved Figure 53 ............................................................................. 25

Changes to Serial Port Interface (SPI) Section ........................... 27

Changes to Table 15 ....................................................................... 28

Changes to Reading the Memory Map Table Section ............... 29

Added Applications Information and

Design Guidelines Sections ...................................................... 32

Changes to Input Signals Section ................................................. 33

Changes to Output Signals Section .............................................. 33

Changes to Figure 60...................................................................... 33

Changes to Default Operation and Jumper Selection

Settings Section .......................................................................... 34

Changes to Alternative Analog Input Drive

Configuration Section............................................................... 35

Added Figure 62 and Figure 63 .................................................... 35

Changes to Figure 68...................................................................... 42

Changes to Table 17 ....................................................................... 48

Updated Outline Dimensions ....................................................... 52

Changes to Ordering Guide .......................................................... 52

10/06—Revision 0: Initial Version

Rev. E | Page 2 of 52

Recommended Resources

One of the small transistor trigger circuits output by pulse transformer

Application of LM3886 in home theater 01

Acute coronary insufficiency alarm circuit

Magnetic sensor amplifier circuit

CT computer room intercom circuit diagram

555 TV automatic shutdown controller circuit

How to solve the problem of LCD screen voltage being too low and black screen restarting when the test bench is turned on?: The test bench is powered by a 5V switching power supply, and many wife, Bluetooth, and zigbee experimental modules are connected. Among them, there is an ARM core board with a 7-inch LCD screen. The ...; 297229936 Analogue and Mixed Signal

Is there an LCD that operates the same as 12864 but has a faster response speed?: Because I don't know how to use tft, I want to use 12864 to make an oscilloscope, but when the frequency is high, 12864 is a bit slow to respond. Is there an LCD that operates the same as 12864 but ha...; zdd563 51mcu

Recommended high-quality code resources (VI) --- The Tragedy of Code: [i=s]This post was last edited by tiankai001 on 2015-2-27 17:07[/i] [align=center] [size=5][b] The Tragedy of Code[/b][/size][/align] [b][size=4]Editor's Recommendation[/size][/b][p=26, 2, left][color...; tiankai001 Download Centre

FPGA and PCI9056 interface problem help!: [font=Arial][size=4]I am working on the interface between FPGA and PCI9056 recently. PCI9056 works in C mode (slave mode and DMA mode). The data sheet says that the number of data that PCI9056 reads a...; lzl19860420 FPGA/CPLD

Hardware can also be more reliable - Introduction to Windows Logo Course on WinHEC: First of all, let's talk about what the Windows Logo Program is. The Windows Logo Program is like a "manufacturer certified accessory" for cars. The hardware and drivers you get are tested and certifi...; 副团长夫人 Talking

Two Atmega8s realize full-duplex communication via SPI interrupt mode: (Single byte transmission) [img]http://fmn033.xnimg.cn/fmn033/pic001/20090226/22/20/large_IKII_56518g206109.jpg[/img] [i] From the simulation, we can see that the data received by the host is the data...; yang_swust Microchip MCU

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components