HIGH SPEED 128K X 8 DUAL CHIP
ENABLE CMOS STATIC RAM
FEATURES
High Speed (Equal Access and Cycle Times)
— 15/20/25/35 ns (Commercial/Industrial)
— 20/25/35/45/55/70/85/100/120 ns (Military)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using
CE
1,
CE
2
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast t
OE
Automatic Power Down
Packages
—32-Pin 300 mil DIP and SOJ
—32-Pin 400 mil SOJ
—32-Pin 600 mil Ceramic DIP
—32-Pin 400 mil Ceramic DIP
—32-Pin Solder Seal Flatpack
—32-Pin LCC (450 x 550 mil)
—32-Pin LCC (400 x 820 mil) [Two-Sided]
—32-Pin Ceramic SOJ
P4C1024
DESCRIPTION
The P4C1024 is a 1,048,576-bit high-speed CMOS
static RAM organized as 128Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 15 nanoseconds permit greatly enhanced
system operating speeds. CMOS is utilized to reduce
power consumption to a low level. The P4C1024 is a
member of a family of PACE RAM™ products offering
fast access times.
The P4C1024 device provides asynchronous operations
with matching access and cycle times. Memory locations
are specified on address pins A
0
to A
16
. Reading is ac-
complished by device selection (CE
1
low and CE
2
high)
and output enabling (OE) while write enable (WE) remains
HIGH. By presenting the address under these conditions,
the data in the addressed memory location is presented
on the data input/output pins. The input/output pins stay
in the HIGH Z state when either
CE
1
or
OE
is HIGH or
WE
or CE
2
is LOW.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (P300, C10, C11),
SOJ (J300, J400, CJ1),
LCC (L1),
SOLDER SEAL
FLATPACK (FS-3) SIMILAR
LCC (L6)
Document #
SRAM124
REV 05
Revised September 2019
P4C1024 - HIGH SPEED 128K X 8 DUAL CHIP ENABLE CMOS STATIC RAM
MAXIMUM RATINGS
(1)
Sym
V
CC
V
TERM
T
A
Parameter
Power Supply Pin with Re-
spect to GND
Terminal Voltage with Re-
spect to GND (up to 7.0V)
Operating Temperature
Value
-0.5 to +7
-0.5 to V
CC
+0.5
-55 to +125
Unit
V
V
°C
Sym
T
BIAS
T
STG
P
T
I
OUT
Parameter
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
-55 to +125
-65 to +150
1.0
50
Unit
°C
°C
W
mA
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
(2)
Military
Industrial
Commercial
CAPACITANCES
(4)
Sym Parameter
C
IN
C
OUT
V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz
Conditions Typ. Unit
V
IN
=0V
V
OUT
=0V
8
10
pF
pF
Input Capacitance
Output Capacitance
Ambient
Temperature
–55°C to +125°C
–40°C to +85°C
0°C to +70°C
GND
0V
0V
0V
V
CC
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
DC ELECTRICAL CHARACTERISTICS
Sym Parameter
V
IH
V
IL
V
HC
V
LC
V
CD
V
OL
V
OH
I
LI
I
LO
I
SB
Input High Voltage
Input Low Voltage
CMOS Input High
Voltage
CMOS Input Low
Voltage
Input Clamp Diode
Voltage
Output Low Voltage
(TTL Load)
V
CC
= Min, I
IN
= -18mA
I
OL
= +8 mA, V
CC
= Min
Over recommended operating temperature and supply voltage
(2)
Test Conditions
P4C1024
Min
2.2
-0.5
(3)
V
CC
- 0.2
-0.5
(3)
P4C1024L
Min
2.2
-0.5
(3)
V
CC
- 0.2
-0.5
(3)
Max
V
CC
+ 0.5
0.8
V
CC
+ 0.5
0.2
-1.2
0.4
Max
V
CC
+ 0.5
0.8
V
CC
+ 0.5
0.2
-1.2
0.4
Unit
V
V
V
V
V
V
V
Output High Voltage
I
OH
= -4 mA, V
CC
= Min
(TTL Load)
Input Leakage Cur-
rent
Output Leakage
Current
V
CC
= Max
V
IN
= GND to V
CC
V
CC
= Max,
CE
= V
IH
,
V
OUT
= GND to V
CC
Mil
Ind / Com'l
Mil
Ind / Com'l
Mil
Ind / Com'l
Mil
Ind / Com'l
2.4
-10
-5
-10
-5
—
—
—
—
+10
+5
+10
+5
35
30
25
20
2.4
-5
n/a
-5
n/a
—
—
—
—
+5
n/a
+5
n/a
25
n/a
2
n/a
µA
µA
mA
Standby Power
CE
1
≥ V
IH
or CE
2
≤ V
IL
,
Supply Current (TTL
V
CC
= Max,
Input Levels)
f = Max, Outputs Open
Standby Power
Supply Current
(CMOS Input
Levels)
CE
1
≥ V
HC
or CE
2
≤ V
LC
,
V
CC
= Max,
f = 0, Outputs Open,
V
IN
≤ V
LC
or V
IN
≥ V
HC
I
SB1
mA
Notes:
1. Stresses greater than those listed under
MAXIMUM RATINGS
may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
Document #
SRAM124
REV 05
Page 2
P4C1024 - HIGH SPEED 128K X 8 DUAL CHIP ENABLE CMOS STATIC RAM
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
Parameter
Temperature
Range
Commercial
I
CC
Dynamic
Operating
Current*
Industrial
Military
-15
190
N/A
N/A
-20
160
175
150
-25
150
165
140
-35
145
160
135
-45
N/A
155
130
-55
N/A
N/A
125
-70
N/A
N/A
115
-85
N/A
N/A
110
-100 -120
N/A
N/A
105
N/A
N/A
100
Unit
mA
mA
mA
*V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
1
= V
IL
, CE
2
= V
IH
,
OE
= V
IH
DATA RETENTION CHARACTERISTICS (P4C1024L)
Symbol Parameter
V
DR
I
CCDR
t
CDR
t
R†
*
T
A
= +25°C
§
†
Test Condition
Min
2.0
2.0V
50
Typ* V
CC
=
3.0V
200
2.0V
400
Max V
CC
=
3.0V
600
Unit
V
µA
ns
ns
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention
Time
Operation Recovery Time
CE
1
≥
V
CC
– 0.2V or
CE
2
≤
0.2V, V
IN
≥
V
CC
– 0.2V
or V
IN
≤
0.2V
0
t
RC§
t
RC
= Read Cycle Time
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
Document #
SRAM124
REV 05
Page 3
P4C1024 - HIGH SPEED 128K X 8 DUAL CHIP ENABLE CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
-15
-20
-25
-35
-45
-55
-70
-85
-100
-120
Sym Parameter
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
20
15
20
25
25
35
35
45
45
55
55
70
70
85
85
100
100
120
120
ns
ns
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
t
OLZ
t
OHZ
Read Cycle Time 15
Address Access
Time
Chip Enable
Access Time
Output Hold from
Address Change
Chip Enable to
Output in Low Z
Chip Disable to
Output in High Z
Output Enable
Low to Data Valid
Output Enable
Low to Low Z
Output Enable
High to High Z
Chip Enable to
15
20
25
35
45
55
70
85
100
120
ns
3
3
3
3
3
3
3
3
3
3
ns
3
3
3
3
3
3
3
3
3
3
ns
8
9
11
15
20
25
30
35
40
50
ns
7
9
11
15
20
25
30
35
40
50
ns
0
0
0
0
0
0
0
0
0
0
ns
7
9
11
15
20
25
30
35
40
50
ns
t
PU
Power Up Time
t
PD
to Power Down
Time
Chip Disable
0
0
0
0
0
0
0
0
0
0
ns
12
20
20
20
25
30
35
40
45
50
ns
Document #
SRAM124
REV 05
Page 4
P4C1024 - HIGH SPEED 128K X 8 DUAL CHIP ENABLE CMOS STATIC RAM
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)
(5)
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)
(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE
1
, CE
2
CONTROLLED)
(5,7,10)
Notes:
5.
WE
is HIGH for READ cycle.
6.
CE
1
is LOW, CE
2
is HIGH and
OE
is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with
CE
1
transition
LOW and CE
2
transition HIGH.
8. Transition is measured ± 200 mV from steady state voltage prior
to change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. READ Cycle Time is measured from the last valid address to the first
transitioning address.
10. Transitions caused by a chip enable control have similar delays
irrespective of whether
CE
1
or CE
2
causes them.
Document #
SRAM124
REV 05
Page 5
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