QL6325E-7PT280I datasheet, PDF

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QL6325E-7PT280I: DescriptionField Programmable Gate Array, 1536 CLBs, 320640 Gates, 1536-Cell, CMOS, PBGA280, 17 X 17 MM, 0.80 MM PITCH, MO-205, LFBGA-280; CategoryProgrammable logic devices Programmable logic; File Size744KB，56 Pages; ManufacturerQuickLogic Corporation; Websitehttps://www.quicklogic.com

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QL6325E-7PT280I Overview

Field Programmable Gate Array, 1536 CLBs, 320640 Gates, 1536-Cell, CMOS, PBGA280, 17 X 17 MM, 0.80 MM PITCH, MO-205, LFBGA-280

QL6325E-7PT280I Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	QuickLogic Corporation
Parts packaging code	BGA
package instruction	LFBGA, BGA280,19X19,32
Contacts	280
Reach Compliance Code	compliant
Combined latency of CLB-Max	1.2446 ns
JESD-30 code	S-PBGA-B280
length	17 mm
Humidity sensitivity level	3
Configurable number of logic blocks	1536
Equivalent number of gates	320640
Number of entries	310
Number of logical units	1536
Output times	310
Number of terminals	280
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	1536 CLBS, 320640 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Encapsulate equivalent code	BGA280,19X19,32
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.8/3.3,2.5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum supply voltage	2.7 V
Minimum supply voltage	2.3 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	17 mm

QL6325E-7PT280I Preview

QL6325E Eclipse-E Data Sheet

••••••

FPGA Combining Performance, Density, and Embedded RAM

Device Highlights

Flexible Programmable Logic

• 0.18 µm six layer metal CMOS process

• 1.8/2.5/3.3 V drive capable I/O

• 1536 logic cells

• Up to 4,002 flip-flops

• Up to 310 I/O pins

• Up to 335 user-available pins

• 320,460 maximum system gates

Advanced Clock Network

• Nine global clock networks:

One dedicated

Eight programmable

• 20 quad-net networks—five per quadrant

• 16 I/O controls—two per I/O bank

• Four phase locked loops

Embedded Computational Units

Twelve ECUs provide integrated Multiply, Add, and

Accumulate functions.

Embedded Dual Port SRAM

• Twenty-four 2,304-bit dual port high

performance SRAM blocks

• 55,296 RAM bits

• RAM/ROM/FIFO wizard for automatic

configuration

• Configurable and cascadable

Security Features

The QuickLogic products come with secure

ViaLink technology that protects intellectual

property from design theft and reverse engineering.

No external configuration memory needed;

instant-on at power-up.

Figure 1: QL6325E Eclipse-E Block Diagram

PLL

Embedded RAM Blocks

Embeded Computational Units

PLL

Programmable I/O

• High performance I/O cell

• Programmable slew rate control

• Programmable I/O standards:

LVTTL, LVCMOS, LVCMOS18, PCI, GTL+,

SSTL2, and SSTL3

Eight independent I/O banks

Three register configurations: Input, Output,

and Output Enable

Fabric

PLL

Embedded RAM Blocks

PLL

www.quicklogic.com

•

QL6325E Eclipse-E Data Sheet Rev. F

QuickWorks Design Software

The QuickWorks package provides the most complete ESP and FPGA software solution from design entry

to logic synthesis, to place and route, to power calculation, and simulation. The package provides a solution

for designers who use third-party tools from Cadence, Mentor, OrCAD, Synopsys, Viewlogic, and other third-

party tools for design entry, synthesis, or simulation.

Programmable Logic Architectural Overview

The Eclipse-E logic cell structure is presented in

Figure 2.

This architectural feature addresses today's register-

intensive designs.

Table 1: Performance Standards

Function

Multiplexer

Parity Tree

Counter

Description

16:1

16 bit

32 bit

128 x 32

FIFO

Clock-to-Out

System clock

128 x 64

256 x 16

Slowest Speed Grade

2.8 ns

3.4 ns

4.6 ns

275 MHz

250 MHz

197 MHz

188 MHz

208 MHz

4 ns

200 MHz

Fastest Speed Grade

2.4 ns

2.9 ns

3.9 ns

328 MHz

300 MHz

235 MHz

266 MHz

248 MHz

3.3 ns

300 MHz

The Eclipse-E logic cell structure presented in

Figure 2

is a dual register, multiplexor-based logic cell. It is

designed for wide fan-in and multiple, simultaneous output functions. Both registers share CLK, SET, and

RESET inputs. The second register has a two-to-one multiplexer controlling its input. The register can be

loaded from the NZ output or directly from a dedicated input.

NOTE:

The input PP is not an “input” in the classical sense. It is a static input to the logic cell and selects

which path (NZ or PS) is used as an input to the Q2Z register. All other inputs are dynamic and can

be connected to multiple routing channels.

The complete logic cell consists of two six-input AND gates, four two-input AND gates, seven two-to-one

multiplexers, and two D flip-flops with asynchronous SET and RESET controls. The cell has a fan-in of 30

(including register control lines), fits a wide range of functions with up to 17 simultaneous inputs, and has six

outputs (four combinatorial and two registered). The high logic capacity and fan-in of the logic cell

accommodates many user functions with a single level of logic delay while other architectures require two or

more levels of delay.

•

www.quicklogic.com

•

QL6325E Eclipse-E Data Sheet Rev. F

Figure 2: Eclipse-E Logic Cell

Q2Z

RAM Modules

The QL6325E includes 24 dual-port 2,304-bit RAM modules for implementing RAM, ROM, and FIFO

functions. Each module is user-configurable into four different block organizations and can be cascaded

horizontally to increase their effective width, or vertically to increase their effective depth as shown in

Figure 4.

Figure 3: 2,304-bit RAM Module

MODE[1:0]

WA[9:0]

WD[17:0]

WCLK

ASYNCRD

RA[9:0]

RD[17:0]

RCLK

Using the two “mode” pins, designers can configure each module into 128 x 18 and 256 x 9. The blocks are

also easily cascadable to increase their effective width and/or depth (see

Figure 4

)

www.quicklogic.com

•

QL6325E Eclipse-E Data Sheet Rev. F

Figure 4: Cascaded RAM Modules

WDATA

WADDR

RAM

Module

(2,304 bits)

RDATA

RADDR

WDATA

RAM

Module

(2,304 bits)

RDATA

The RAM modules are dual-port, with completely independent READ and WRITE ports and separate READ

and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE

ports support synchronous operation. Each port has 18 data lines and 8 address lines, allowing word lengths

of up to 18 bits and address spaces of up to 256 words. Depending on the mode selected, however, some

higher order data or address lines may not be used.

The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable (RE) acts

as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through enable for

asynchronous READ operation (ASYNCRD input high).

Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by

connecting corresponding address lines together and dividing the words between modules.

A similar technique can be used to create depths greater than 256 words. In this case address signals higher

than the MSB are encoded onto the write enable (WE) input for WRITE operations. The READ data outputs

are multiplexed together using encoded higher READ address bits for the multiplexer SELECT signals.

The RAM blocks can be loaded with data generated internally (typically for RAM or FIFO functions) or with

data from an external PROM (typically for ROM functions).

Embedded Computational Unit (ECU)

Traditional Programmable Logic architectures do not implement arithmetic functions efficiently or effectively—

these functions require high logic cell usage while garnering only moderate performance results.

The Eclipse-E architecture allows for functionality above and beyond that achievable using programmable logic

devices. By embedding a dynamically reconfigurable computational unit, the Eclipse-E device can address

various arithmetic functions efficiently. This approach offers greater performance and utilization than

traditional programmable logic implementations. The embedded block is implemented at the transistor level

as shown in

Figure 5.

•

www.quicklogic.com

•

QL6325E Eclipse-E Data Sheet Rev. F

Figure 5: ECU Block Diagram

RESET

CIN

SIGN1

SIGN2

01 3-1

mux

Q[16:0]

3-4

decoder

A[7:0]

A[15:8]

8-bit

Multiplier

2-1

mux

16-bit

Adder

17-bit

A[0:15]

CLK

B[0:15]

2-1

mux

The Eclipse-E ECU block (Table

is placed next to the SRAM circuitry for efficient memory/instruction fetch

and addressing for DSP algorithmic implementations.

Table 2: Eclipse-E ECU Block

Device

QL6325E

ECUs

Up to twelve 8-bit MAC functions can be implemented per cycle for a total of 1.2 billion MACs/s when clocked

at 100 MHz. Additional multiply-accumulate functions can be implemented in the programmable logic.

The modes for the ECU block are dynamically re-programmable through the programmable logic.

www.quicklogic.com

•

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QL6325E-7PT280I Related Products

	QL6325E-7PT280I	QL6325E-6PT280C	QL6325E-6PT280I	QL6325E-6PT280M	QL6325E-7PT280C	QL6325E-7PT280M	QL6325E-8PT280C	QL6325E-8PT280I	QL6325E-8PT280M
Description	Field Programmable Gate Array, 1536 CLBs, 320640 Gates, 1536-Cell, CMOS, PBGA280, 17 X 17 MM, 0.80 MM PITCH, MO-205, LFBGA-280	Field Programmable Gate Array, 1536 CLBs, 320640 Gates, 1536-Cell, CMOS, PBGA280, 17 X 17 MM, 0.80 MM PITCH, MO-205, LFBGA-280	Field Programmable Gate Array, 1536 CLBs, 320640 Gates, 1536-Cell, CMOS, PBGA280, 17 X 17 MM, 0.80 MM PITCH, MO-205, LFBGA-280	Field Programmable Gate Array, 1536 CLBs, 320640 Gates, 1536-Cell, CMOS, PBGA280, 17 X 17 MM, 0.80 MM PITCH, MO-205, LFBGA-280	Field Programmable Gate Array, 1536 CLBs, 320640 Gates, 1536-Cell, CMOS, PBGA280, 17 X 17 MM, 0.80 MM PITCH, MO-205, LFBGA-280	Field Programmable Gate Array, 1536 CLBs, 320640 Gates, 1536-Cell, CMOS, PBGA280, 17 X 17 MM, 0.80 MM PITCH, MO-205, LFBGA-280	Field Programmable Gate Array, 1536 CLBs, 320640 Gates, 1536-Cell, CMOS, PBGA280, 17 X 17 MM, 0.80 MM PITCH, MO-205, LFBGA-280	Field Programmable Gate Array, 1536 CLBs, 320640 Gates, 1536-Cell, CMOS, PBGA280, 17 X 17 MM, 0.80 MM PITCH, MO-205, LFBGA-280	Field Programmable Gate Array, 1536 CLBs, 320640 Gates, 1536-Cell, CMOS, PBGA280, 17 X 17 MM, 0.80 MM PITCH, MO-205, LFBGA-280
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	QuickLogic Corporation	QuickLogic Corporation	QuickLogic Corporation	QuickLogic Corporation	QuickLogic Corporation	QuickLogic Corporation	QuickLogic Corporation	QuickLogic Corporation	QuickLogic Corporation
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	LFBGA, BGA280,19X19,32	LFBGA, BGA280,19X19,32	LFBGA, BGA280,19X19,32	LFBGA, BGA280,19X19,32	LFBGA, BGA280,19X19,32	LFBGA, BGA280,19X19,32	LFBGA, BGA280,19X19,32	LFBGA, BGA280,19X19,32	LFBGA, BGA280,19X19,32
Contacts	280	280	280	280	280	280	280	280	280
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant
Combined latency of CLB-Max	1.2446 ns	1.3622 ns	1.3916 ns	1.4896 ns	1.2152 ns	1.323 ns	1.1368 ns	1.1662 ns	1.2446 ns
JESD-30 code	S-PBGA-B280	S-PBGA-B280	S-PBGA-B280	S-PBGA-B280	S-PBGA-B280	S-PBGA-B280	S-PBGA-B280	S-PBGA-B280	S-PBGA-B280
length	17 mm	17 mm	17 mm	17 mm	17 mm	17 mm	17 mm	17 mm	17 mm
Configurable number of logic blocks	1536	1536	1536	1536	1536	1536	1536	1536	1536
Equivalent number of gates	320640	320640	320640	320640	320640	320640	320640	320640	320640
Number of entries	310	310	310	310	310	310	310	310	310
Number of logical units	1536	1536	1536	1536	1536	1536	1536	1536	1536
Output times	310	310	310	310	310	310	310	310	310
Number of terminals	280	280	280	280	280	280	280	280	280
Maximum operating temperature	85 °C	70 °C	85 °C	125 °C	70 °C	125 °C	70 °C	85 °C	125 °C
Minimum operating temperature	-40 °C	-	-40 °C	-55 °C	-	-55 °C	-	-40 °C	-55 °C
organize	1536 CLBS, 320640 GATES	1536 CLBS, 320640 GATES	1536 CLBS, 320640 GATES	1536 CLBS, 320640 GATES	1536 CLBS, 320640 GATES	1536 CLBS, 320640 GATES	1536 CLBS, 320640 GATES	1536 CLBS, 320640 GATES	1536 CLBS, 320640 GATES
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFBGA	LFBGA	LFBGA	LFBGA	LFBGA	LFBGA	LFBGA	LFBGA	LFBGA
Encapsulate equivalent code	BGA280,19X19,32	BGA280,19X19,32	BGA280,19X19,32	BGA280,19X19,32	BGA280,19X19,32	BGA280,19X19,32	BGA280,19X19,32	BGA280,19X19,32	BGA280,19X19,32
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	225	NOT SPECIFIED
power supply	1.8/3.3,2.5 V	1.8/3.3,2.5 V	1.8/3.3,2.5 V	1.8/3.3,2.5 V	1.8/3.3,2.5 V	1.8/3.3,2.5 V	1.8/3.3,2.5 V	1.8/3.3,2.5 V	1.8/3.3,2.5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.5 mm	1.5 mm	1.5 mm	1.5 mm	1.5 mm	1.5 mm	1.5 mm	1.5 mm	1.5 mm
Maximum supply voltage	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
Minimum supply voltage	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V
Nominal supply voltage	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	MILITARY	COMMERCIAL	MILITARY	COMMERCIAL	INDUSTRIAL	MILITARY
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	17 mm	17 mm	17 mm	17 mm	17 mm	17 mm	17 mm	17 mm	17 mm
Humidity sensitivity level	3	3	3	-	3	-	3	3	-

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