PCA9545BS datasheet, PDF - EEWORLD Datasheet

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PCA9545BS: DescriptionBus Controller, PQCC20; CategoryThe embedded processor and controller Microcontrollers and processors; File Size149KB，17 Pages; ManufacturerPhilips Semiconductors (NXP Semiconductors N.V.); Websitehttps://www.nxp.com/; Environmental Compliance

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PCA9545BS Overview

Bus Controller, PQCC20

PCA9545BS Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Philips Semiconductors (NXP Semiconductors N.V.)
Reach Compliance Code	unknown
JESD-30 code	S-PQCC-N20
JESD-609 code	e4
Number of terminals	20
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	QCCN
Encapsulate equivalent code	LCC20,.20SQ,25
Package shape	SQUARE
Package form	CHIP CARRIER
power supply	2.5/5 V
Certification status	Not Qualified
Maximum slew rate	0.6 mA
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	NO LEAD
Terminal pitch	0.635 mm
Terminal location	QUAD

PCA9545BS Preview

INTEGRATED CIRCUITS

PCA9545

4-channel I

C switch with interrupt logic

and reset

Product data sheet

Supersedes data of 2002 Dec 13

2004 Sep 29

Philips

Semiconductors

Philips Semiconductors

Product data sheet

4-channel I

C switch with interrupt logic and reset

PCA9545

DESCRIPTION

The PCA9545 is a quad bi-directional translating switch controlled

via the I

C-bus. The SCL/SDA upstream pair fans out to four

downstream pairs, or channels. Any individual SCx/SDx channel or

combination of channels can be selected, determined by the

contents of the programmable control register. Four interrupt inputs,

INT0 to INT3, one for each of the downstream pairs, are provided.

One interrupt output, INT, acts as an AND of the four interrupt

inputs.

FEATURES

•

1-of-4 bi-directional translating switches

•

C interface logic; compatible with SMBus standards

•

4 active LOW interrupt inputs

•

Active LOW interrupt output

•

Active LOW reset input

•

2 address pins allowing up to 4 devices on the I

C-bus

•

Channel selection via I

C-bus, in any combination

•

Power up with all switch channels deselected

•

Low RDS

switches

•

Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and

•

No glitch on power-up

•

Supports hot insertion

•

Low stand-by current

•

Operating power supply voltage range of 2.3 V to 5.5 V

•

5 V tolerant Inputs

•

0 kHz to 400 kHz clock frequency

•

ESD protection exceeds 2000 V HBM per JESD22-A114,

•

Latch-up testing is done to JESDEC Standard JESD78 which

•

Three packages offered: SO20, TSSOP20, and HVQFN20

ORDERING INFORMATION

PACKAGES

20-Pin Plastic SO

20-Pin Plastic TSSOP

20-Pin Plastic HVQFN

TEMPERATURE RANGE

–40

°C

to +85

°C

–40

°C

to +85

°C

–40

°C

to +85

°C

exceeds 100 mA

150 V MM per JESD22-A115 and 1000 V per JESD22-C101

5 V buses

An active-LOW reset input allows the PCA9545 to recover from a

situation where one of the downstream I

C-buses is stuck in a LOW

state. Pulling the RESET pin LOW resets the I

C state machine and

causes all the channels to be deselected as does the internal power

on reset function.

The pass gates of the switches are constructed such that the V

pin can be used to limit the maximum high voltage which will be

passed by the PCA9545. This allows the use of different bus

voltages on each pair, so that 1.8 V or 2.5 V or 3.3 V parts can

communicate with 5 V parts without any additional protection.

External pull-up resistors pull the bus up to the desired voltage level

for each channel. All I/O pins are 5 V tolerant.

ORDER CODE

PCA9545D

PCA9545PW

PCA9545BS

DRAWING NUMBER

SOT163-1

SOT360-1

SOT662-1

Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.

2004 Sep 29

Philips Semiconductors

Product data sheet

4-channel I

C switch with interrupt logic and reset

PCA9545

PIN CONFIGURATION — SO, TSSOP

A0 1

A1 2

RESET 3

INT0 4

SD0 5

SC0 6

INT1 7

SD1 8

SC1 9

20 V

19 SDA

18 SCL

17 INT

16 SC3

15 SD3

14 INT3

13 SC2

PIN CONFIGURATION — HVQFN

A0 V

SDA SCL

15 INT

14 SC3

13 SD3

12 INT3

11 SC2

RESET

INT0

SD0

SC0

INT1

12 SD2

11 INT2

SD1 SC1 V

INT2 SD2

SW00762

TOP VIEW

SW02016

Figure 1. Pin configuration — SO, TSSOP

Figure 2. Pin configuration — HVQFN

PIN DESCRIPTION

SO, TSSOP

PIN NUMBER

HVQFN

PIN NUMBER

SYMBOL

RESET

INT0

SD0

SC0

INT1

SD1

SC1

INT2

SD2

SC2

INT3

SD3

SC3

INT

SCL

SDA

Address input 0

Address input 1

Active LOW reset input

Active LOW interrupt input 0

Serial data 0

Serial clock 0

Active LOW interrupt input 1

Serial data 1

Serial clock 1

Supply ground

Active LOW interrupt input 2

Serial data 2

Serial clock 2

Active LOW interrupt input 3

Serial data 3

Serial clock 3

Active LOW interrupt output

Serial clock line

Serial data line

Supply voltage

FUNCTION

2004 Sep 29

Philips Semiconductors

Product data sheet

4-channel I

C switch with interrupt logic and reset

PCA9545

BLOCK DIAGRAM

PCA9545

SC0

SC1

SC2

SC3

SD0

SD1

SD2

SD3

SWITCH CONTROL LOGIC

RESET

POWER ON

RESET

SCL

INPUT

FILTER

C-BUS

CONTROL

SDA

INT[0–3]

INT LOGIC

INT

SW00758

Figure 3. Block diagram

2004 Sep 29

Philips Semiconductors

Product data sheet

4-channel I

C switch with interrupt logic and reset

PCA9545

DEVICE ADDRESS

Following a START condition the bus master must output the

address of the slave it is accessing. The address of the PCA9545 is

shown in Figure 4. To conserve power, no internal pullup resistors

are incorporated on the hardware selectable address pins and they

must be pulled HIGH or LOW.

FIXED

A1 A0 R/W

CONTROL REGISTER DEFINITION

One or several SCx/SDx downstream pair, or channel, is selected

by the contents of the control register. This register is written after

the PCA9545 has been addressed. The 2 LSBs of the control byte

are used to determine which channel is to be selected. When a

channel is selected, the channel will become active after a stop

condition has been placed on the I

C-bus. This ensures that all

SCx/SDx lines will be in a HIGH state when the channel is made

active, so that no false conditions are generated at the time of

connection.

Table 1. Control Register; Write — Channel Selection/

Read — Channel Status

INT3

INT2

INT1

INT0

HARDWARE SELECTABLE

SW00893

Figure 4. Slave address

The last bit of the slave address defines the operation to be

performed. When set to logic 1, a read is selected while a logic 0

selects a write operation.

COMMAND

Channel 0

disabled

Channel 0

enabled

Channel 1

disabled

Channel 1

enabled

Channel 2

disabled

Channel 2

enabled

Channel 3

disabled

Channel 3

enabled

No channel

selected;

power-up/

reset default

state

CONTROL REGISTER

Following the successful acknowledgement of the slave address,

the bus master will send a byte to the PCA9545, which will be stored

in the control register. If multiple bytes are received by the

PCA9545, it will save the last byte received. This register can be

written and read via the I

C-bus.

INTERRUPT BITS

(READ ONLY)

CHANNEL SELECTION BITS

(READ/WRITE)

CHANNEL

INT0

INT1

INT2

INT3

INT3 INT2 INT1 INT0

SW00949

Figure 5. Control Register

NOTE:

Several channels can be enabled at the same time.

Ex: B3 = 0, B2 = 1, B1 = 1, B0 = 0, means that channel 0 and 3 are

disabled and channel 1 and 2 are enabled.

Care should be taken not to exceed the maximum bus capacity.

2004 Sep 29

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