CMOS/TTL into 4 Low Voltage Differential Signaling
(LVDS) data streams while the transmit clock input is
transmitted in parallel with the data streams over a fifth
LVDS link. The V385 can be programmed for rising
edge or falling edge clocks through pin R_FB.
ICS manufactures a large variety of video application
devices. Consult ICS for all of your video application
requirements.
Features
•
Packaged in a 56-pin TSSOP (Pb free available)
•
Convert 28 bits of 3.3 V CMOS/TTL into 4 LVDS
streams
•
Up to 2.38 Gbps throughput or 297.5 Megabytes/sec
bandwidth
Pin Assignment
VCC
TxIN5
TxIN6
TxIN7
GND
TxIN8
TxIN9
TxIN10
VCC
TxIN11
TxIN12
TxIN13
GND
TxIN14
TxIN15
TxIN16
R_FB
TxIN17
TxIN18
TxIN19
GND
TxIN20
TxIN21
TxIN22
TxIN23
VCC
TxIN24
TxIN25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
TxIN4
TxIN3
TxIN2
GND
TxIN1
TxIN0
TxIN27
LVDS_GND
TxOUT0-
TxOUT0+
TxOUT1-
TxOUT1+
LVDS_VCC
LVDS_GND
TxOUT2-
TxOUT2+
TxCLKOUT-
TxCLKOUT+
TxOUT3-
TxOUT3+
LVDS_GND
PLL_GND
PLL_VCC
PLL_GND
PWRDWN
TxCLKIN
TxIN26
GND
•
•
•
•
•
•
•
•
•
Wide clock frequency range from 20 MHz to 85 MHz
Supports VGA, SVGA, XGA, and SXGA
LVDS voltage swing of 350 mV for low EMI
On-chip PLL requires no external components
Single 3.3 V low-power CMOS design
Programmable rising or falling edge strobe
Power-down control function
Compatible with TIA/EIA-644 LVDS standards
Pin and function compatible with the National
DS90C385, TI SN65LVDS93 and THine
THC63LVDM83
Block Diagram
Red, Green, Blue
HSYNC
VSYNC
DATA ENABLE
CONTROL
R_FB
PWRDWN
CLOCK
PLL
TTL to
LVDS
24
TxOUT0+
TxOUT0-
TxOUT1+
TxOUT1-
TxOUT2+
TxOUT2-
TxOUT3+
TxOUT3-
TxCLKOUT+
TxCLKOUT-
56-pin TSSOP
V385 Datasheet
1
8/30/2004
Revision 1.3
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
V385
8-B
IT
LVDS T
RANSMITTER FOR
V
IDEO
Pin Descriptions
Pin
Type
VCC
Pin
Count
5
Pins
1, 9, 26,34, 44
Pin Description/Name
3 pins for Logic and Data TTL inputs (VCC, 3.3 V power supply).
1 pins for PLL (PLL_VCC).
1 pin for LVDS (LVDS_VCC).
5 pins for Logic and Data TTL inputs(GND).
2 pins for PLL (PLL_GND).
3 pins for LVDS input pairs (LVDS_GND).
Parallel digital video input pins (TxIN0..27).
GND
10
5, 13, 21, 29, 33, 35,
36, 43, 49, 53
2, 3, 4, 6, 7, 8, 10, 11,
12, 14, 15, 16, 18, 19,
20, 22, 23, 24, 25, 27,
28, 30, 50, 51, 52, 54,
55, 56
37, 38, 39, 40, 41, 42,
45, 46, 47, 48
31
17
32
CMOS/TTL
28
LVDS Differential
Ouput
CMOS/TTL
Prgrammable
Strobe Select
Power Down
10
1
1
1
8 pins (4 pairs) for Serialized video data (TxOUT0..3+/-).
2 pins (1 pair) for clock outputs (TxCLKOUT+/-)
Clock input (TxCLKIN)
Programmable strobe select input pin (R_FB). High = rising
edge; Low = falling edge.
Active low (PWRDWN). Power-down tri-states outputs.
External Components
The V385 requires no external components.
V385 Datasheet
2
8/30/2004
Revision 1.3
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
V385
8-B
IT
LVDS T
RANSMITTER FOR
V
IDEO
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the V385. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Electrostatic Discharge (EIAJ, 0Ω, 200 pF)
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
-0.3 V to +4 V
-0.3 V to VCC+0.3 V
> 500 V
0 to +70°C
-65 to +150°C
150°C
230°C
Rating
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
3.0
Typ.
3.3
Max.
+70
3.6
Units
°C
V
SMT IR-Profile
Sn/Pb :63/37 183
o
C
300
270
240
210
180
TEMP C
o
Peak Temp.
230±10
o
C
Tg
150
120
90
60
30
0
0
30
60
90
120
150
180
210
240
270
300
330
360
390
TIME(SECS)
Preheat
Melting
Cooling
Inital
V385 Datasheet
3
8/30/2004
Revision 1.3
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
V385
8-B
IT
LVDS T
RANSMITTER FOR
V
IDEO
Electrical Characteristics
VDD=3.3 V ±10%,
Ambient temperature 0 to +70°C
Parameter
CMOS/TTL DC Specifications
Input High Voltage
Input Low Voltage
Input Current
Power-down Current
LVDS DC Specifications
Differential Output Voltage
Change in V
OD
Between
Complimentary Output States
Common Mode Voltage
Change in V
OC
Between
Complimentary Output States
Output Short Circuit Current
Output Tri-State Current
Transmitter Supply Current
Transmitter Supply Current
(worst case)
Transmitter Supply Current
(16 Grayscale)
I
TCCW
I
TCCG
R
L
= 100 ohms, C
L
=5 pF,
worst case pattern
R
L
= 100 ohms, C
L
=5 pF,
16 Grayscale pattern
mA
mA
mA
mA
5
11.76
0.35T
0.35T
1.5
0.75
0.75
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
-0.2
T/7-0.2
2T/7-0.2
3T/7-0.2
4T/7-0.2
5T/7-0.2
6T/7-0.2
2.5
0
T/7
2T/7
3T/7
4T/7
5T/7
6T/7
T
0.5T
0.5T
50
0.65T
0.65T
6
1.5
1.5
0.2
T/7+0.2
2T/7+0.2
3T/7+0.2
4T/7+0.2
5T/7+0.2
6T/7+0.2
10
ns
ns
ns
ns
ns
ns
ns
0.2
ns
ns
ns
ns
ns
ns
ms
ns
85 MHz
85 MHz
85 MHz
85 MHz
85 MHz
85 MHz
85 MHz
65 MHz
85 MHz
65 MHz
85 MHz
V
OD
DV
OD
V
OC
DV
OC
I
OS
I
OZ
V
OD
=0V
Power Down#=0V
3.5
12
1.125
1.250
R
L
= 100 ohms
250
345
450
35
1.375
35
5
mV
mV
V
mV
mA
µA
V
IH
V
IL
I
IN
I
PD
GND<VIN<VCC
No switching for input pins
2.00
GND
VCC
0.80
±10
10
V
V
µA
µA
Symbol
Conditions
Min.
Typ.
Max.
Units
Freq.
Recommended Transmitter Input Characteristics
TxCLK IN Transition Time
TxCLK IN Period
TxCLK IN High Time
TxCLK IN Low Time
TxIN Transition Time
LVDS Low-to-High Time
LVDS High-to-Low Time
Transmitter Output Pulse
Position
TCIT
TCIP
TCIH
TCIL
TXIT
LLHT
LHLT
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
Transmitter Phase Loop Set
TxIN Setup to TxCLK IN
TPLLS
TSTC
Transmitter Switching Characteristics
V385 Datasheet
4
8/30/2004
Revision 1.3
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
V385
8-B
IT
LVDS T
RANSMITTER FOR
V
IDEO
Parameter
TxIN Hold to TxCLK IN
TxCLK IN to TxCLK OUT
Delay
Transmitter Jitter
Cycle-to-Cycle
Symbol
THTC
TCCD
TJCC
Conditions
Min.
0
1T/7+0.8
Typ.
Max.
1T/7+3.4
Units
ns
ns
ps
ps
ps
Freq.
350
210
110
370
230
150
40 MHz
65 MHZ
85 MHz
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
θ
JA
θ
JA
θ
JA
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
84
76
67
50
Max.
Units
°C/W
°C/W
°C/W
°C/W
Thermal Resistance Junction to Case
θ
JC
AC Timing Diagrams
TCIP
TCIL
TxCLK IN
TxIN
TCIH
THTC
TCIH
Figure AC1. Transmitter Setup/Hold and High/Low Times (Falling Edge Strobe or R_FB=0)
TxCLK IN
TxCLK OUT+
TCCD
TxCLK OUT-
Figure AC2. Clock IN to Clock OUT Delay (Rising Edge Strobe or R_FB=1)
V385 Datasheet
5
8/30/2004
Revision 1.3
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
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