MX23C1010
1M-BIT MASK ROM (8 BIT OUTPUT)
FEATURES
• Bit organization
- 128K x 8 (byte mode)
• Fast access time
- Random access: 45ns (max.)
• Current
- Operating: 40mA
- Standby: 100uA
• Supply voltage
- 5V±10% for 70ns(max.)
- 5V±5% for 45ns(max.)
• Package
- 32 pin PDIP/SOP/PLCC/TSOP
ORDER INFORMATION
Part No.
MX23C1010PC-45
MX23C1010PC-70
MX23C1010PC-90
MX23C1010PC-10
MX23C1010PC-12
MX23C1010PC-15
MX23C1010MC-45
MX23C1010MC-70
Access Time
45ns
70ns
90ns
100ns
120ns
150ns
45ns
70ns
Package
32 pin PDIP
32 pin PDIP
32 pin PDIP
32 pin PDIP
32 pin PDIP
32 pin PDIP
32 pin SOP
32 pin SOP
32 pin SOP
32 pin SOP
32 pin SOP
32 pin SOP
32 pin PLCC
32 pin PLCC
32 pin PLCC
32 pin PLCC
32 pin PLCC
32 pin PLCC
32 pin TSOP
32 pin TSOP
32 pin TSOP
32 pin TSOP
32 pin TSOP
32 pin TSOP
32 pin PLCC
32 pin PLCC
32 pin TSOP
PIN CONFIGURATION
32 PDIP
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
NC
NC
A14
A13
A8
A9
A11
OE
A10
CE
D7
D6
D5
D4
D3
32 SOP
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
VSS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
10
19
18
17
VCC
NC
NC
A14
A13
A8
A9
A11
OE
A10
CE
D7
D6
D5
D4
D3
MX23C1010MC-90 90ns
MX23C1010MC-10 100ns
MX23C1010MC-12 120ns
MX23C1010MC-15 150ns
MX23C1010QC-45 45ns
MX23C1010QC-70 70ns
MX23C1010QC-90 90ns
MX23C1010QC-10 100ns
MX23C1010QC-12 120ns
MX23C1010QC-15 150ns
MX23C1010TC-45
45ns
MX23C1010TC-70
70ns
MX23C1010TC-90
90ns
MX23C1010TC-10
100ns
MX23C1010TC-12
120ns
MX23C1010TC-15
150ns
MX23C1010QI-12(*) 120ns
MX23C1010QI-15(*) 150ns
MX23C1010TI-90(*) 90ns
(*): industrial grade, TA= -40° C ~ 85° C
MX23C1010
MX231010
PIN DESCRIPTION
Symbol
A0~A16
D0~D7
CE
OE
VCC
VSS
NC
Pin Function
Address Inputs
Data Outputs
Chip Enable Input
Output Enable Input
Power Supply Pin
Ground Pin
No Connection
REV. 4.0, DEC. 10, 1998
P/N:PM0227
1
MX23C1010
32 TSOP(I)
32 PLCC
VCC
A12
A15
A16
NC
NC
NC
30
29
VSS
D1
D2
D3
D4
D5
ABSOLUTE MAXIMUM RATINGS
ITEM
Voltage on any Pin Relative to VSS
Ambient Operating Temperature
Storage Temperature
SYMBOL
VIN
Topr
Tstg
RATINGS
-0.5V to 7.0V
-40°C to 85°C
-65°C to 125°C
DC CHARACTERISTICS
(Ta = -40°C ~ 85°C, VCC = 5V±10% for 70ns max., 5V±5% for 45ns max.)
ITEM
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Standby Current (TTL)
Standby Current (CMOS)
Input Capacitance
Output Capacitance
SYMBOL
VOH
VOL
VIH
VIL
ILI
ILO
ICC1
ISTB1
ISTB2
CIN
COUT
MIN.
2.4V
-
2.0V
-0.3V
-10
-10
-
-
-
-
-
MAX.
-
0.4V
VCC+0.5V
0.8V
10uA
10uA
40mA
1.5mA
100uA
12pF
12pF
CONDITIONS
IOH = -0.4mA
IOL = 2.1mA
VIN=0 to 5.5V
VOUT=0 to 5.5V
CE = VIL, f = 5MHz, Iout = 0mA
CE = VIH
CE = VCC +/- 0.3V
VIN=0V
VOUT=OV
P/N:PM0227
REV. 4.0, DEC. 10, 1998
2
D6
A11
A9
A8
A13
A14
NC
NC
VCC
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MX23C1010
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
D7
D6
D5
D4
D3
VSS
D2
D1
D0
A0
A1
A2
A3
A7
A6
A5
A4
A3
A2
A1
A0
D0
5
4
1
32
A14
A13
A8
A9
9
MX23C1010
25
A11
OE
A10
CE
13
14
17
21
20
D7
MX23C1010
AC CHARACTERISTICS
(Ta = -40°C ~ 85°C, VCC = 5V±10% for 70ns max., 5V±5% for 45ns max.)
ITEM
SYMBOL
23C1010-45*
MIN.
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Time
tRC
tAA
tACE
tOE
45ns
-
-
-
0ns
-
MAX.
-
45ns
45ns
25ns
-
17ns
23C1010-70*
MIN.
70ns
-
-
-
0ns
-
MAX.
-
70ns
70ns
35ns
-
20ns
23C1010-90
MIN.
90ns
-
-
-
0ns
-
MAX.
-
90ns
90ns
40ns
-
25ns
23C1010-10
MIN.
100ns
-
-
-
0ns
-
MAX.
-
100ns
100ns
45ns
-
30ns
23C1010-12
MIN
120ns
-
-
-
0ns
-
MAX
-
120ns
120ns
50ns
-
35ns
23C1010-15
MIN
150ns
-
-
-
0ns
-
MAX
-
150ns
150ns
60ns
-
50ns
Output Hold After Address tOH
Output High Z Delay
tHZ
Note :Output high-impedance delay (tHZ) is measured from OE or CE going high, and this parameter guaranteed by
design over the full voltage and temperature operating range - not tested.
*45ns&70ns speed grades are under development.
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Level
Output Timing Level
Output Load
0.4V~2.4V
0V~3v (for 45ns&70ns)
10ns
0.8V~2.0V
1.5V (for 45ns&70ns)
0.8V and 2.0V
1.5V (for 45ns&70ns)
See Figure
DEVICE
UNDER
TEST
CL=100pF*
1.8K ohm
+5V
6.2K ohm
DIODES = IN3064
OR EQUIVALENT
*CL=30pF for 45ns&70ns
TIMING DIAGRAM
RANDOM READ
ADD
ADD
tACE
ADD
tRC
ADD
CE
OE
tOE
tOH
VALLID
tHZ
VALLID
tAA
DATA
VALLID
Note : CE, OE are enable.
P/N:PM0227
REV. 4.0, DEC. 10, 1998
3
MX23C1010
PACKAGE INFORMATION
32-PIN PLASTIC DIP (600 mil)
ITEM
A
B
C
D
E
F
G
H
I
J
K
L
M
MILLIMETERS
42.13 max.
1.90 [REF]
2.54 [TP]
.46 [Typ.]
38.07
1.27 [Typ.]
3.30±.25
.51 [REF]
3.94±.25
5.33 max.
15.22±.25
13.97±.25
.25 [Typ.]
INCHES
1.660 max.
.075 [REF]
.100 [TP]
.018 [Typ.]
1.500
.050 [Typ.]
.130±.010
.020 [REF]
.155±.010
.210 max.
.600±.010
.550±.010
.010 [Typ.]
32
17
1
A
16
K
L
I
H
F
D
E
J
G
C
B
M
0~15
NOTE:
Each lead centerline is located within .25 mm[.01
inch] of its true position [TP] at maximum material condition.
32-PIN PLASTIC SOP (450 mil)
ITEM
A
B
C
D
E
F
G
H
I
J
K
L
MILLIMETERS
20.95 max.
1.00 [REF]
1.27 [TP]
.40 [Typ.]
.05 min.
3.05 max.
2.69±.13
14.12±.25
11.30±.13
1.42
.20 [Typ.]
.79
INCHES
.825 max.
.039 [REF]
.050 [TP]
.016 [Typ.]
.002 min.
.120 max.
.106±.005
.556±.010
.445±.005
.056
.008 [Typ.]
.031
32
17
1
A
16
H
I
J
G
F
K
E
NOTE:
Each lead centerline is located within .25 mm[.01
inch] of its true position [TP] at maximum material condition.
D
C
B
L
P/N:PM0227
REV. 4.0, DEC. 10, 1998
4
MX23C1010
32-PIN PLASTIC TSOP
ITEM
A
B
C
D
E
F
G
H
I
J
K
L
M
N
MILLIMETERS
20.0±.20
18.40±.10
8.20 max.
.15 [Typ.]
.80 [Typ.]
.20±.10
.30±.10
.50 [Typ.]
.45 max.
0 ~ .20
1.00±.10
1.27 max.
.50
0 ~ 5°
INCHES
.078±.006
.724±.004
.323 max.
.006 [Typ.]
.031 [Typ.]
.008±.004
C
A
B
.012±.004
.020 [Typ.]
.018 max.
0 ~ .008
.039±.004
.050 max.
.020
.500
D
E
F
G
H
I
J
K
L
N
M
NOTE:
Each lead centerline is located within .25 mm[.01
inch] of its true position [TP] at maximum material condition.
32-PIN PLASTIC LEADED CHIP CHARRIER (PLCC)
A
ITEM
A
B
C
D
E
F
G
H
I
J
K
L
MILLIMETERS
12.44±.13
11.50±.13
14.04±.13
14.98±.13
1.93
3.30±.25
2.03±.13
.51±.13
1.27 [Typ.]
.71 [REF]
.46 [REF]
10.40/12.94
(W)
(L)
INCHES
.490±.005
.453±.005
.553±.13
.590±.13
.076
.130±.010
.080±.005
.020±.005
.050 [Typ.]
.028 [REF]
.018 [REF]
.410/.510
(W)
(L)
13
14
9
5
4
B
1
32
30
29
25
C
D
21
20
E
17
M
N
.89 R
.25 [TYP.]
.035 R
.010 [TYP.]
F
G
N
H
I
K
L
M
J
NOTE:
Each lead centerline is located within .25 mm[.01
inch] of its true position [TP] at maximum material condition.
P/N:PM0227
REV. 4.0, DEC. 10, 1998
5
京公网安备 11010802033920号
EEWORLD
