128K x 36
3.3V Synchronous ZBT™ SRAM
2.5V I/O, Burst Counter
Pipelined Outputs
◆
◆
◆
◆
◆
◆
71V2546S
Features
128K x 36 memory configurations
Supports high performance system speed - 150 MHz
(3.8 ns Clock-to-Data Access)
ZBT
TM
Feature - No dead cycles between write and read
cycles
Internally synchronized output buffer enable eliminates the
need to control
OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
◆
◆
◆
◆
◆
◆
◆
4-word burst capability (interleaved or linear)
Individual byte write (BW
1
-
BW
4
) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%), 2.5V I/O Supply (V
DDQ)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP) and 119 ball grid array (BGA)
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
LBO
Address A [0:16]
CE1,
CE,
CE2
R/W
CEN
ADV/LD
BWx
D
Clk
D
Q
Control
D
Q
128Kx36 BIT
MEMORY ARRAY
Address
Input Register
DI
DO
Q
Control Logic
Mux
Sel
D
Clk
Clock
Output Register
Q
OE
Gate
5294 drw 01a
Data I/O [0:31],
I/O P[1:4]
ZBT and ZeroBus Turnaround are trademarks of Renesas and the architecture is supported by Micron Technology and Motorola Inc.
1
Aug.12.20
71V2546, 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Description
The IDT71V2546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAM. It is designed to eliminate dead bus cycles when
turning the bus around between reads and writes, or writes and reads.
Thus, they have been given the name ZBT
TM
, or Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one clock
cycle, and two cycles later the associated data cycle occurs, be it read
or write.
The IDT71V2546 contains data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V2546 to be
suspended as long as necessary. All synchronous inputs are ignored
when (CEN) is high and the internal device registers will hold their previous
values.
There are three chip enable pins (CE
1
, CE
2
,
CE
2
) that allow the user
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state two cycles after chip is deselected or a write is
initiated.
The IDT71V2546 has an on-chip burst counter. In the burst mode, the
IDT71V2546 can provide four cycles of data for a single address
presented to the SRAM. The order of the burst sequence is defined by the
LBO
input pin. The
LBO
pin selects between linear and interleaved burst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
The IDT71V2546 SRAM utilizes a high-performance CMOS process
and is packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic
quad flatpack (TQFP) as well as a 119 ball grid array (BGA).
Pin Description Summary
A
0
-A
16
CE
1
, CE
2
,
CE
2
OE
R/
W
CEN
BW
1
,
BW
2
,
BW
3
,
BW
4
CLK
ADV/
LD
LBO
ZZ
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
V
DD
, V
DDQ
V
SS
Ad d re ss Inp uts
Chip Enab le s
Outp ut Enab le
Re ad /Write Sig nal
Clo ck Enab le
Ind ivid ual Byte Write Se le cts
Clo ck
Ad vance b urst ad d re ss / Lo ad ne w ad d re ss
Line ar / Inte rle ave d Burst Ord e r
S le e p Mo d e
Data Inp ut / Outp ut
Co re Po we r, I/O Po we r
Gro und
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
I/O
Sup p ly
Sup p ly
Synchro no us
Synchro no us
Asynchro no us
Synchro no us
Synchro no us
Synchro no us
N/A
Synchro no us
Static
Synchro no us
Synchro no us
Static
Static
5294 tb l 01
6.42
2
Aug.12.20
71V2546 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Definitions
(1)
Symbol
A
0
-A
16
ADV/
LD
Pin Function
Ad d re ss Inp uts
Ad vance / Lo ad
I/O
I
I
Active
N/A
N/A
Description
Synchro no us Ad d re ss inp uts. The ad d re ss re g iste r is trig g e re d b y a co mb inatio n o f the rising e d g e o f CLK,
ADV/
LD
lo w,
CEN
lo w, and true chip e nab le s.
ADV/
LD
is a synchro no us inp ut that is use d to lo ad the inte rnal re g iste rs with ne w ad d re ss and co ntro l whe n it
is samp le d lo w at the rising e d g e o f clo ck with the chip se le cte d . Whe n ADV/
LD
is lo w with the chip
d e se le cte d , any b urst in p ro g re ss is te rminate d . Whe n ADV/
LD
is samp le d hig h the n the inte rnal b urst co unte r
is ad vance d fo r any b urst that was in p ro g re ss. The e xte rnal ad d re sse s are ig no re d whe n ADV/
LD
is samp le d
hig h.
R/
W
sig nal is a synchro no us inp ut that id e ntifie s whe the r the curre nt lo ad cycle initiate d is a Re ad o r Write
acce ss to the me mo ry array. The d ata b us activity fo r the curre nt cycle take s p lace two clo ck cycle s late r.
Synchro no us Clo ck Enab le Inp ut. Whe n
CEN
is samp le d hig h, all o the r synchro no us inp uts, includ ing clo ck
are ig no re d and o utp uts re main unchang e d . The e ffe ct o f
CEN
samp le d hig h o n the d e vice o utp uts is as if the
lo w to hig h clo ck transitio n d id no t o ccur. Fo r no rmal o p e ratio n,
CEN
must b e samp le d lo w at rising e d g e o f
c lo c k .
Synchro no us b yte write e nab le s. Each 9-b it b yte has its o wn active lo w b yte write e nab le . On lo ad write cycle s
(Whe n R/
W
and ADV/
LD
are samp le d lo w) the ap p ro p riate b yte write sig nal (
BW
1
-
BW
4
) must b e valid . The
b yte write sig nal must also b e valid o n e ach cycle o f a b urst write . Byte Write sig nals are ig no re d whe n R/
W
is
samp le d hig h. The ap p ro p riate b yte (s) o f d ata are writte n into the d e vice two cycle s late r.
BW
1
-
BW
4
can all b e
tie d lo w if always d o ing write to the e ntire 36-b it wo rd .
Synchro no us active lo w chip e nab le .
CE
1
and
CE
2
are use d with CE
2
to e nab le the IDT71V2546. (
CE
1
o r
CE
2
samp le d hig h o r CE
2
samp le d lo w) and ADV/
LD
lo w at the rising e d g e o f clo ck, initiate s a d e se le ct cycle . The
ZBT
TM
has a two cycle d e se le ct, i.e ., the d ata b us will tri-state two clo ck cycle s afte r d e se le ct is initiate d .
Synchro no us active hig h chip e nab le . CE
2
is use d with
CE
1
and
CE
2
to e nab le the chip . CE
2
has inve rte d
p o larity b ut o the rwise id e ntical to
CE
1
and
CE
2
.
This is the clo ck inp ut to the IDT71V2546. Exce p t fo r
OE
, all timing re fe re nce s fo r the d e vice are mad e with
re sp e ct to the rising e d g e o f CLK.
Synchro no us d ata inp ut/o utp ut (I/O) p ins. Bo th the d ata inp ut p ath and d ata o utp ut p ath are re g iste re d and
trig g e re d b y the rising e d g e o f CLK.
Burst o rd e r se le ctio n inp ut. Whe n
LBO
is hig h the Inte rle ave d b urst se q ue nce is se le cte d . Whe n
LBO
is lo w
the Line ar b urst se q ue nce is se le cte d .
LBO
is a static inp ut and it must no t chang e d uring d e vice o p e ratio n.
Asynchro no us o utp ut e nab le .
OE
must b e lo w to re ad d ata fro m the IDT71V2546. Whe n
OE
is hig h the I/O p ins
are in a hig h-imp e d ance state .
OE
d o e s no t ne e d to b e active ly co ntro lle d fo r re ad and write cycle s. In no rmal
o p e ratio n,
OE
can b e tie d lo w.
Synchro no us sle e p mo d e inp ut. ZZ HIGH will g ate the CLK inte rnally and p o we r d o wn the IDT71V2546 to its
lo we st p o we r co nsump tio n le ve l. Data re te ntio n is g uarante e d in Sle e p Mo d e . This p in has an inte rnal
p ulld o wn.
3.3V co re p o we r sup p ly.
2.5V I/O Sup p ly.
Gro und .
5294 tb l 02
R/
W
CEN
Re ad / Write
Clo ck Enab le
I
I
N/A
LOW
BW
1
-
BW
4
Ind ivid ual Byte
Write Enab le s
I
LOW
CE
1
,
CE
2
Chip Enab le s
I
LOW
CE
2
CLK
I/O
0
-I/O
31
I/O
P1
-I/O
P4
LBO
OE
Chip Enab le
Clo ck
Data Inp ut/Outp ut
Line ar Burst Ord e r
Outp ut Enab le
I
I
I/O
I
I
HIGH
N/A
N/A
LOW
LOW
ZZ
V
DD
V
DDQ
V
SS
S le e p Mo d e
Po we r Sup p ly
Po we r Sup p ly
Gro und
I
N/A
N/A
N/A
HIGH
N/A
N/A
N/A
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
3
Aug.12.20
71V2546, 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration
(3)
— 128K x 36, PKG100
CE
2
BW
4
BW
3
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
NC
A
8
A
9
A
6
A
7
CE
1
I/O
P3
I/O
16
I/O
17
V
DDQ
V
SS
I/O
18
I/O
19
I/O
20
I/O
21
V
SS
V
DDQ
I/O
22
I/O
23
V
DD
(1)
V
DD
V
DD
(1)
V
SS
I/O
24
I/O
25
V
DDQ
V
SS
I/O
26
I/O
27
I/O
28
I/O
29
V
SS
V
DDQ
I/O
30
I/O
31
I/O
P4
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5294 drw 02
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
71V2546
PKG100
I/O
P2
I/O
15
I/O
14
V
DDQ
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DDQ
I/O
9
I/O
8
V
SS
V
DD
(1)
V
DD
V
SS/ZZ
(2)
I/O
7
I/O
6
V
DDQ
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DDQ
I/O
1
I/O
0
I/O
P1
,
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to V
DD
as long as the input voltage is
≥
V
IH
.
2. Pin 64 does not have to be connected directly to V
SS
as long as the input voltage is
≤
V
IL
; on the latest die revision this pin supports ZZ (sleep mode).
3, This text does not indicate the orientation of actual part-marking..
Aug.12.20
LBO
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
10
A
11
A
12
A
13
A
14
A
15
A
16
Top View
100 TQFP
6.42
4
71V2546 128K x 36, 3.3V Synchronous ZBT™ SRAM
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration
(3)
— 128K x 36, BG119
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
I/O
16
I/O
17
V
DDQ
I/O
20
I/O
22
V
DDQ
I/O
24
I/O
25
V
DDQ
I/O
29
I/O
31
NC
NC
V
DDQ
2
A
6
CE
2
A
7
I/O
P3
I/O
18
I/O
19
I/O
21
I/O
23
V
DD
I/O
26
I/O
27
I/O
28
I/O
30
I/O
P4
A
5
NC
NC
3
A
4
A
3
A
2
V
SS
V
SS
V
SS
BW
3
V
SS
V
DD(1)
V
SS
BW
4
V
SS
V
SS
V
SS
LBO
A
10
NC
4
NC
ADV/LD
V
DD
NC
CE
1
OE
NC
R/W
V
DD
CLK
NC
CEN
A
1
A
0
V
DD
A
11
NC
5
A
8
A
9
A
12
V
SS
V
SS
V
SS
BW
2
V
SS
V
DD(1)
V
SS
BW
1
V
SS
V
SS
V
SS
V
DD(1)
A
14
NC
6
A
16
CE
2
A
15
I/O
P2
I/O
13
I/O
12
I/O
11
I/O
9
V
DD
I/O
6
I/O
4
I/O
3
I/O
2
I/O
P1
A
13
NC
NC
7
V
DDQ
NC
NC
I/O
15
I/O
14
V
DDQ
I/O
10
I/O
8
V
DDQ
I/O
7
I/O
5
V
DDQ
I/O
1
I/O
0
NC
NC/ZZ
(2)
V
DDQ
5294 drw 13a
,
Top View
119 BGA
NOTES:
1. J3, J5, and R5 do not have to be directly connected to V
DD
as long as the input voltage is
≥
V
IH
.
2. Pin T7 supports ZZ (sleep mode) on the latest die revision.
3. This text does not indicate orientation of actual part-marking.
6.42
5
Aug.12.20
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