840N071BGILF datasheet, PDF - EEWORLD Datasheet

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840N071BGILF: DescriptionClock Generator, 159.38MHz, CMOS, PDSO8, 4.40 X 3 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-8; CategoryThe embedded processor and controller Microcontrollers and processors; File Size517KB，13 Pages; ManufacturerIDT (Integrated Device Technology)

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840N071BGILF Overview

Clock Generator, 159.38MHz, CMOS, PDSO8, 4.40 X 3 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-8

840N071BGILF Parametric

Parameter Name	Attribute value
Maker	IDT (Integrated Device Technology)
package instruction	TSSOP,
Reach Compliance Code	compliant
ECCN code	EAR99
JESD-30 code	R-PDSO-G8
length	4.4 mm
Number of terminals	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	159.38 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Master clock/crystal nominal frequency	26.5625 MHz
Maximum seat height	1.2 mm
Maximum supply voltage	3.465 V
Minimum supply voltage	2.375 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
width	3 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER

840N071BGILF Preview

FemtoClock

NG Crystal-to-LVCMOS/LVTTL

Clock Synthesizer

General Description

The ICS840N071I is a LVCMOS/LVTTL clock synthesizer designed

for Serial ATA (SAS)/Serial Attached SCSI (SAS) applications. The

device generates a selectable 150MHz or 75MHz clock signal with

excellent phase jitter performance. The device uses IDT’s fourth

generation FemtoClock

NG technology for an optimum of high

clock frequency, low phase noise performance and low power

consumption.The device supports 2.5V or 3.3V voltage supply and is

packaged in a small, lead-free (RoHS 6) 8-lead TSSOP package.

The extended temperature range supports wireless infrastructure,

telecommunication and networking end equipment requirements.

ICS840N071I

DATA SHEET

Features

•

Fourth generation FemtoClock

NG technology

150MHz output clock synthesized from a 25MHz fundamental

mode crystal

One 2.5V or 3.3V LVCMOS/LVTTL clock output

Crystal interface designed for 25MHz,

12pF parallel resonant crystal

RMS phase jitter @ 150MHz, using a 25MHz crystal

(12kHz - 20MHz): 0.453ps (maximum)

RMS phase jitter @ 75MHz, using a 25MHz crystal

(12kHz - 20MHz): 0.456ps (maximum)

LVCMOS interface levels for the control inputs

Full 2.5V or 3.3V supply voltage

Available in lead-free (RoHS 6) package

-40°C to 85°C ambient operating temperature

FREQ_SEL Frequency Table

Input

FREQ_SEL

1 (default)

Output Frequency

XTAL

= 25MHz

150MHz

75MHz

XTAL

= 26.5625MHz

159.375MHz

79.6875MHz

NOTE: FREQ_SEL is an asynchronous control.

OE Function Table

Input

1 (default)

Output Enable

Output Q is disabled in high-impedance state

Output Q is enabled.

NOTE: OE is an asynchronous control.

Block Diagram

XTAL_IN

OSC

XTAL_OUT

PFD

LPF

FemtoClock

VCO

490-637.50MHz

÷4,

÷8

Pin Assignment

VDDA

XTAL_OUT

XTAL_IN

VDD

GND

FREQ_SEL

÷24

FREQ_SEL

Pullup

ICS840N071I

8-lead TSSOP

4.40mm x 3.0mm x 0.925mm

package body

G Package

Top View

ICS840N071BGI REVISION A MAY 25, 2012

ICS840N071I Data Sheet

FEMTOCLOCK

NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER

Table 1. Pin Descriptions

Number

Name

DDA

XTAL_OUT,

XTAL_IN

FREQ_SEL

GND

Power

Input

Power

Output

Power

Pulldown

Pullup

Type

Description

Analog power supply.

Output enable pin. LVCMOS interface levels.

Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.

Frequency select pin. LVCMOS interface levels.

Power supply ground.

Single-ended clock output. LVCMOS/LVTTL interface levels.

Core supply pin.

NOTE:

Pulldown and Pullup

refer to internal input resistors. See Table 2,

Pin Characteristics,

for typical values.

Table 2. Pin Characteristics

Symbol

PULLUP

PULLDOWN

OUT

Parameter

Input Capacitance

Power Dissipation

Capacitance

Input Pullup Resistor

Input Pulldown Resistor

Output Impedance

= 3.3V

= 2.5V

= 3.465V

= 2.625V

Test Conditions

Minimum

Typical

3.5

Maximum

Units



ICS840N071BGI REVISION A MAY 25, 2012

ICS840N071I Data Sheet

FEMTOCLOCK

NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under

Absolute Maximum Ratings

may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the

DC Characteristics or AC Characteristics

is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

Item

Supply Voltage, V

Inputs, V

Outputs, I

Continuous Current

Surge Current

Package Thermal Impedance,



Storage Temperature, T

STG

Rating

3.63V

-0.5V to V

+ 0.5V

50mA

100mA

117°C/W (0 mps)

-65C to 150C

DC Electrical Characteristics

Table 3A. Power Supply DC Characteristics, V

= 3.3V±5% or 2.5V±5%, T

= -40°C to 85°C

Symbol

DDA

Parameter

Core Supply Voltage

Analog Supply Voltage

Analog Supply Current

Power Supply Current

Test Conditions

Minimum

2.375

– 0.18

Typical

3.3

2.5

Maximum

3.465

Units

Table 3B. LVCMOS/LVTTL DC Characteristics, V

= 3.3V±5% or 2.5V±5%, T

= -40°C to 85°C

Symbol

Parameter

Input High Voltage

Input Low Voltage

FREQ_SEL

Input High Current

FREQ_SEL

Test Conditions

= 3.3V

= 2.5V

= 3.3V

= 2.5V

= V

= 3.465V or 2.625V

= V

= 3.465V or 2.625V

= 3.465V or 2.625V, V

= 0V

= 3.465V or 2.625V, V

= 0V

= 3.465V

= 2.625V

= 3.465V or 2.625V

-5

-150

2.6

1.8

0.5

Minimum

1.7

-0.3

Typical

Maximum

+ 0.3

0.5

0.8

0.5

0.7

150

Units

µA

Input Low Current

Output High Voltage;

NOTE 1

Output Low Voltage;

NOTE 1

NOTE 1: Output terminated with 50



to V

/ 2. See Parameter Measurement Information Section,

LVCMOS Output Load Test Circuit Diagrams.

ICS840N071BGI REVISION A MAY 25, 2012

ICS840N071I Data Sheet

FEMTOCLOCK

NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER

Table 4. Crystal Characteristics

Parameter

Mode of Oscillation

Frequency

Equivalent Series Resistance (ESR)

Shunt Capacitance

20.42

Test Conditions

Minimum

Typical

Fundamental

26.5625

MHz

Maximum

Units



AC Characteristics

Table 5. AC Characteristics, V

= V

DDA

= 3.3V±5% or 2.5V±5%, T

= -40°C to 85°C

Symbol

OUT

Parameter

Output Frequency

Test Conditions

FREQ_SEL = 0

FREQ_SEL = 1

OUT

= 150MHz, 25MHz Crystal,

Integration Range: 12kHz – 20MHz

tjit(Ø)

RMS Phase Jitter (Random);

NOTE 1

OUT

= 75MHz, 25MHz Crystal,

Integration Range: 12kHz – 20MHz

OUT

= 159.375MHz, 26.5625MHz Crystal,

Integration Range: 12kHz – 20MHz

OUT

= 150MHz, Offset: 10Hz

OUT

= 150MHz, Offset: 100Hz



Single-Side Band Noise

Power

OUT

= 150MHz, Offset: 1kHz

OUT

= 150MHz, Offset: 10kHz

OUT

= 150MHz, Offset: 100kHz

OUT

= 150MHz, Offset: 1MHz

OUT

= 150MHz, Offset: 10MHz

/ t

odc

Output Rise/Fall Time

Output Duty Cycle

20% to 80%

200

Minimum

122.50

61.25

Typical

150

0.345

0.343

0.350

-47.0

-76.7

-108.8

-123.5

-131.0

-139.5

-156.6

600

Maximum

159.38

79.69

0.453

0.456

0.486

Units

MHz

dBc/Hz

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device

is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.

NOTE: Characterized with a 25MHz and 26.5625MHz crystal.

NOTE 1: Please refer to the phase noise plots.

ICS840N071BGI REVISION A MAY 25, 2012

ICS840N071I Data Sheet

FEMTOCLOCK

NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER

Typical Phase Noise at 75MHz (12kHz - 20MHz)

Noise Power dBc

Offset Frequency (Hz)

Typical Phase Noise at 150MHz (12kHz - 20MHz)

Noise Power dBc

Offset Frequency (Hz)

ICS840N071BGI REVISION A MAY 25, 2012

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840N071BGILF Related Products

	840N071BGILF	840N071BGILFT
Description	Clock Generator, 159.38MHz, CMOS, PDSO8, 4.40 X 3 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-8	Clock Generator, 159.38MHz, CMOS, PDSO8, 4.40 X 3 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-8
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
package instruction	TSSOP,	TSSOP,
Reach Compliance Code	compliant	compliant
ECCN code	EAR99	EAR99
JESD-30 code	R-PDSO-G8	R-PDSO-G8
length	4.4 mm	4.4 mm
Number of terminals	8	8
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Maximum output clock frequency	159.38 MHz	159.38 MHz
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Master clock/crystal nominal frequency	26.5625 MHz	26.5625 MHz
Maximum seat height	1.2 mm	1.2 mm
Maximum supply voltage	3.465 V	3.465 V
Minimum supply voltage	2.375 V	2.375 V
Nominal supply voltage	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL
width	3 mm	3 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER

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