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7133SA35J

Description
PLCC-68, Tube
Categorystorage    storage   
File Size448KB,18 Pages
ManufacturerIDT (Integrated Device Technology)
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7133SA35J Overview

PLCC-68, Tube

7133SA35J Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codePLCC
package instruction0.950 X 0.950 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-68
Contacts68
Manufacturer packaging codePL68
Reach Compliance Codenot_compliant
ECCN codeEAR99
Maximum access time35 ns
I/O typeCOMMON
JESD-30 codeS-PQCC-J68
JESD-609 codee0
length24.2062 mm
memory density32768 bit
Memory IC TypeDUAL-PORT SRAM
memory width16
Humidity sensitivity level1
Number of functions1
Number of ports2
Number of terminals68
word count2048 words
character code2000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize2KX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC68,1.0SQ
Package shapeSQUARE
Package formCHIP CARRIER
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply5 V
Certification statusNot Qualified
Maximum seat height4.572 mm
Maximum standby current0.015 A
Minimum standby current2 V
Maximum slew rate0.295 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width24.2062 mm
HIGH SPEED
2K X 16 DUAL-PORT
SRAM
7133SA/LA
7143SA/LA
Features
High-speed access
– Military: 35/55/70/90ns (max.)
– Industrial: 25ns (max.)
– Commercial: 20/25/35/45/55/70/90ns (max.)
Low-power operation
– IDT7133/43SA
Active: 1150mW (typ.)
Standby: 5mW (typ.)
– IDT7133/43LA
Active: 1050mW (typ.)
Standby: 1mW (typ.)
Versatile control for write: separate write control for lower
and upper byte of each port
MASTER IDT7133 easily expands data bus width to 32 bits
or more using SLAVE IDT7143
On-chip port arbitration logic (IDT7133 only)
BUSY
output flag on IDT7133;
BUSY
input on IDT7143
Fully asynchronous operation from either port
Battery backup operation–2V data retention
TTL-compatible; single 5V (±10%) power supply
Available in 68-pin ceramic PGA, Flatpack, PLCC and 100-
pin TQFP
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
R/W
LUB
CE
L
R/W
RUB
CE
R
R/W
LLB
OE
L
R/W
RLB
OE
R
I/O
8L
- I/O
15L
I/O
0L
- I/O
7L
BUSY
L
(1)
A
10L
A
0L
ADDRESS
DECODER
11
I/O
CONTROL
I/O
CONTROL
I/O
8R
- I/O
15R
I/O
0R
- I/O
7R
BUSY
R
(1)
MEMORY
ARRAY
ADDRESS
DECODER
11
A
10R
A
0R
CE
L
ARBITRATION
LOGIC
(IDT7133 ONLY)
CE
R
2746 drw 01
NOTE:
1. IDT7133 (MASTER):
BUSY
is open drain output and requires pull-up resistor.
IDT7143 (SLAVE):
BUSY
is input.
AUGUST 2019
1
©2019 Integrated Device Technology, Inc.
DSC 2746/16
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