UJA1065
High-speed CAN/LIN fail-safe system basis chip
Rev. 07 — 25 February 2010
Product data sheet
1. General description
The UJA1065 fail-safe System Basis Chip (SBC) replaces basic discrete components that
are common in every Electronic Control Unit (ECU) with a Controller Area Network (CAN)
and a Local Interconnect Network (LIN) interface. The fail-safe SBC supports all
networking applications that control various power and sensor peripherals by using
high-speed CAN as the main network interface and LIN as a local sub-bus. The fail-safe
SBC contains the following integrated devices:
•
High-speed CAN transceiver, interoperable and downward compatible with CAN
transceivers TJA1041 and TJA1041A, and compatible with the ISO 11898-2 standard
and the ISO 11898-5 standard (in preparation)
•
•
•
•
•
•
LIN transceiver compliant with LIN 2.0 and SAE J2602, and compatible with LIN 1.3
Advanced independent watchdog
Dedicated voltage regulators for microcontroller and CAN transceiver
Serial peripheral interface (full duplex)
Local wake-up input port
Inhibit/limp-home output port
In addition to the advantages of integrating these common ECU functions in a single
package, the fail-safe SBC offers an intelligent combination of system-specific functions
such as:
•
•
•
•
Advanced low-power concept
Safe and controlled system start-up behavior
Advanced fail-safe system behavior that prevents any conceivable deadlock
Detailed status reporting on system and subsystem levels
The UJA1065 is designed to be used in combination with a microcontroller that
incorporates a CAN controller. The fail-safe SBC ensures that the microcontroller is
always started up in a defined manner. In failure situations, the fail-safe SBC will maintain
microcontroller functionality for as long as possible to provide full monitoring and a
software-driven fall-back operation.
The UJA1065 is designed for 14 V single power supply architectures and for 14 V and
42 V dual power supply architectures.
NXP Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
2. Features
2.1 General
Contains a full set of CAN and LIN ECU functions:
CAN transceiver and LIN transceiver
Voltage regulator for the microcontroller (3.3 V or 5.0 V)
Separate voltage regulator for the CAN transceiver (5 V)
Enhanced window watchdog with on-chip oscillator
Serial Peripheral Interface (SPI) for the microcontroller
ECU power management system
Fully integrated autonomous fail-safe system
Designed for automotive applications:
Supports 14 V and 42 V architectures
Excellent ElectroMagnetic Compatibility (EMC) performance
±8
kV ElectroStatic Discharge (ESD) protection Human Body Model (HBM) for
off-board pins
±4
kV ElectroStatic Discharge (ESD) protection IEC 61000-4-2 for off-board pins
±60
V short-circuit proof CAN/LIN-bus pins
Battery and CAN/LIN-bus pins are protected against transients in accordance with
ISO 7637-3
Very low sleep current
Supports remote flash programming via the CAN-bus
Small 6.1 mm
×
11 mm HTSSOP32 package with low thermal resistance
2.2 CAN transceiver
ISO 11898-2 and ISO 11898-5 compliant high-speed CAN transceiver
Enhanced error signalling and reporting
Dedicated low dropout voltage regulator for the CAN-bus:
Independent from microcontroller supply
Guarded by CAN-bus failure management
Significantly improves EMC performance
Partial networking option with global wake-up feature, allows selective CAN-bus
communication without waking up sleeping nodes
Bus connections are truly floating when power is off
SPLIT output pin for stabilizing the recessive bus level
2.3 LIN transceiver
LIN 2.0 compliant LIN transceiver
Enhanced error signalling and reporting
Downward compatible with LIN 1.3 and the TJA1020
UJA1065_7
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 — 25 February 2010
2 of 76
NXP Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
2.4 Power management
Smart operating modes and power management modes
Cyclic wake-up capability in Standby and Sleep mode
Local wake-up input with cyclic supply feature
Remote wake-up capability via the CAN-bus and LIN-bus
External voltage regulators can easily be incorporated in the power supply system
(flexible and fail-safe)
42 V battery-related high-side switch for driving external loads such as relays and
wake-up switches
Intelligent maskable interrupt output
2.5 Fail-safe features
Safe and predictable behavior under all conditions
Programmable fail-safe coded window and time-out watchdog with on-chip oscillator,
guaranteeing autonomous fail-safe system supervision
Fail-safe coded 16-bit SPI interface for the microcontroller
Global enable pin for the control of safety-critical hardware
Detection and detailed reporting of failures:
On-chip oscillator failure and watchdog alerts
Battery and voltage regulator undervoltages
CAN and LIN-bus failures (short-circuits and open-circuit bus wires)
TXD and RXD clamping situations and short-circuits
Clamped or open reset line
SPI message errors
Overtemperature warning
ECU ground shift (two selectable thresholds)
Rigorous error handling based on diagnostics
Supply failure early warning allows critical data to be stored
23 bits of access-protected RAM is available e.g. for logging of cyclic problems
Reporting in a single SPI message; no assembly of multiple SPI frames needed
Limp-home output signal for activating application hardware in case system enters
Fail-safe mode (e.g. for switching on warning lights)
Fail-safe coded activation of Software development mode and Flash mode
Unique SPI readable device type identification
Software-initiated system reset
UJA1065_7
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 — 25 February 2010
3 of 76
NXP Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
3. Ordering information
Table 1.
Ordering information
Package
Name
UJA1065TW
HTSSOP32
Description
Version
plastic thermal enhanced thin shrink small outline package; 32 leads; SOT549-1
body width 6.1 mm; lead pitch 0.65 mm; exposed die pad
Type number
[1]
[1]
UJA1065TW/5V0 is for the 5 V version; UJA1065TW/3V3 is for the 3.3 V version.
4. Block diagram
SENSE
BAT42
BAT14
31
32
27
BAT
MONITOR
V1
UJA1065
4
V1
SYSINH
V3
INH/LIMP
29
30
17
V2
20
V2
INH
V1 MONITOR
INTN
WAKE
TEST
7
18
16
CHIP
TEMPERATURE
SBC
FAIL-SAFE
SYSTEM
WAKE
RESET/EN
6
8
RSTN
EN
WATCHDOG
SCK
SDI
SDO
SCS
11
9
10
12
SPI
GND SHIFT
DETECTOR
OSCILLATOR
RTLIN
LIN
TXDL
RXDL
GND
26
25
3
5
23
LIN
HIGH
SPEED
CAN
BAT42
BAT42
V2
21
22
13
14
24
SPLIT
CANH
CANL
TXDC
RXDC
001aac305
Fig 1.
Block diagram
UJA1065_7
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 — 25 February 2010
4 of 76
NXP Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
5. Pinning information
5.1 Pinning
n.c.
n.c.
TXDL
V1
RXDL
RSTN
INTN
EN
SDI
1
2
3
4
5
6
7
8
9
32 BAT42
31 SENSE
30 V3
29 SYSINH
28 n.c.
27 BAT14
26 RTLIN
25 LIN
24 SPLIT
23 GND
22 CANL
21 CANH
20 V2
19 n.c.
18 WAKE
17 INH/LIMP
001aac306
UJA1065TW
SDO 10
SCK 11
SCS 12
TXDC 13
RXDC 14
n.c. 15
TEST 16
Fig 2.
Pin configuration
5.2 Pin description
Table 2.
Symbol
n.c.
n.c.
TXDL
V1
RXDL
RSTN
INTN
EN
SDI
SDO
SCK
SCS
TXDC
RXDC
n.c.
TEST
UJA1065_7
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
not connected
not connected
LIN transmit data input (LOW for dominant, HIGH for recessive)
voltage regulator output for the microcontroller (3.3 V or 5 V depending on the
SBC version)
LIN receive data output (LOW when dominant, HIGH when recessive)
reset output to microcontroller (active LOW; will detect clamping situations)
interrupt output to microcontroller (active LOW; open-drain, wire-AND this pin to
other ECU interrupt outputs)
enable output (active HIGH; push-pull, LOW with every reset/watchdog
overflow)
SPI data input
SPI data output (floating when pin SCS is HIGH)
SPI clock input
SPI chip select input (active LOW)
CAN transmit data input (LOW for dominant; HIGH for recessive)
CAN receive data output (LOW when dominant; HIGH when recessive)
not connected
test pin (should be connected to ground in application)
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 07 — 25 February 2010
5 of 76
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