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KSZ8081RNAIA

Description
PHY 1-CH 10Mbps/100Mbps 3.3V 24-Pin QFN EP
File Size952KB,53 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Environmental Compliance
Download Datasheet Parametric View All

KSZ8081RNAIA Overview

PHY 1-CH 10Mbps/100Mbps 3.3V 24-Pin QFN EP

KSZ8081RNAIA Parametric

Parameter NameAttribute value
EU restricts the use of certain hazardous substancesCompliant
ECCN (US)EAR99
Part StatusActive
HTS8542.39.00.01
Number of Channels per Chip1
Maximum Data Rate100Mbps
PHY Line Side InterfaceNo
JTAG SupportNo
Integrated CDRNo
Standard Supported10BASE-T|100BASE-TX
Typical Data Rate (MBps)10/100
Ethernet Speed10Mbps/100Mbps
Ethernet Interface TypeMII/RMII
Minimum Operating Supply Voltage (V)3.135
Typical Operating Supply Voltage (V)3.3
Maximum Operating Supply Voltage (V)3.465
Maximum Supply Current (mA)47(Typ)
Power Supply TypeAnalog
Minimum Operating Temperature (°C)-40
Maximum Operating Temperature (°C)85
Supplier Temperature GradeIndustrial
Pin Count24
Standard Package NameQFN
Supplier PackageQFN EP
MountingSurface Mount
Package Height0.83
Package Length4
Package Width4
PCB changed24
Lead ShapeNo Lead
K
KSZ8081
1RNA/KS
SZ8081R
RND
10Bas
se-T/100Ba
ase-TX PHY
Y
w
with RMII Su
upport
Revision 1.2
Gen
neral Desc
cription
The KSZ8081RNA is a single-supply 10Ba
A
ase-T/100Bas
se-
Ethernet phy
ysical-layer tr
ransceiver fo transmission
or
TX E
and reception of data over standard CAT unshielded
s
T-5
ed
)
twiste pair (UTP) cable.
The KSZ8081RNA is a highly
y-integrated PHY solution. It
P
ces
st
out
o
reduc board cos and simplifies board layo by using on-
chip termination resistors for the differentia pairs and by
r
t
al
r
e
integrating a low-noise regulator to supply the 1.2V core, and
ffering 1.8/2.5
5/3.3V digital I/O interface support.
s
by of
The K
KSZ8081RNA offers the Reduced Med Independe
A
R
dia
ent
Interf
face (RMII) for direct co
f
onnection to RMII-complia
ant
MAC in Ethernet processors and switches.
Cs
t
a
As th power-up default, the KSZ8081RNA uses a 25MH
he
d
K
A
Hz
cryst
tal to generate all requ
uired clocks, including the
Hz
erence clock output for the MAC. The
50MH RMII refe
KSZ8
8081RND is the version th takes in th 50MHz RM
t
hat
he
MII
refere
ence clock as the power-u default.
s
up
To fa
acilitate syste bring-up and debugging in production
em
a
testin and in pro
ng
oduct deploym
ment, parame
etric NAND tree
supp
port enables fault detection between KSZ8081RN
NA
®
I/Os and the boa
ard. Micrel’s LinkMD TD
DR-based cab
ble
nostics identif faulty copper cabling.
fy
diagn
The KSZ8081RNA and KSZ80
A
081RND are available in 24-
a
2
N
see
pin, lead-free QFN packages (s
Ordering Information).
Datasheets and support docu
s
umentation ar available on
re
el’s
a
el.com.
Micre web site at:
www.micre
Featu
ures
Sing
gle-chip 10Ba
ase-T/100Bas
se-TX IEEE 80
02.3
com
mpliant Ethern transceive
net
er
RMI v1.2 Interface support with a 50MHz r
II
reference
ck
MAC, and an o
option to input a 50MHz
cloc output to M
refe rence clock
RMI back-to-bac mode supp for a 100M
II
ck
port
Mbps copper
eater
repe
MDC
C/MDIO mana
agement inte
erface for PHY register
Y
conf
figuration
Prog
grammable in
nterrupt outpu
ut
LED outputs for link and activi status indic
D
ity
cation
On-c
chip termination resistors f the differe
for
ential pairs
Bas eline wander correction
HP A
Auto MDI/MD
DI-X to reliably detect and c
y
correct
straiight-through a crossove cable conne
and
er
ections with
disa
able and enab option
ble
Auto
o-negotiation to automatica select the highest link-
ally
e
-
up s
speed (10/100
0Mbps) and d
duplex (half/fu
ull)
Pow
wer-down and power-saving modes
d
Link
kMD TDR-bas cable diag
sed
gnostics to identify faulty
copp cabling
per
Para
ametric NAND Tree suppo for fault de
D
ort
etection
betw
ween chip I/O and the boa
Os
ard
Fun
nctional Diagram
MD
ed
M
LinkM is a registere trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Driv • San Jose, CA 95131 • USA • tel +1 (408) 94
ve
C
44-0800 • fax + 1 (408) 474-1000 •
http://www.m
0
micrel.com
December 10, 2014
4
Revision 1.2

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