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ISL8487, ISL81483, ISL81487
Pinout
ISL8487, ISL81483, ISL81487 (PDIP, SOIC)
TOP VIEW
INPUTS
RO 1
RE 2
DE 3
DI 4
D
R
8
7
6
5
V
CC
B/Z
A/Y
GND
Truth Tables
TRANSMITTING
OUTPUTS
DI
1
0
X
X
Z
0
1
High-Z
High-Z *
Y
1
0
High-Z
High-Z *
RE
X
X
0
1
DE
1
1
0
0
*Shutdown Mode for ISL8487, ISL81483 (see Note 7)
RECEIVING
INPUTS
RE
0
0
0
1
1
DE
0
0
0
0
1
A-B
≥
+0.2V
≤
-0.2V
Inputs Open
X
X
OUTPUT
RO
1
0
1
High-Z *
High-Z
*Shutdown Mode for ISL8487, ISL81483 (see Note 7)
Ordering Information
PART NO.
ISL8487IB
ISL8487IBZ (Note)
ISL8487IP
ISL8487IPZ (Note)
ISL81483IB
ISL81483IBZ (Note)
ISL81483IP
ISL81483IPZ (Note)
ISL81487IB
ISL81487IBZ (Note)
ISL81487IP
ISL81487IPZ (Note)
PART MARKING
8487IB
8487IBZ
ISL8487IP
8487IPZ
81483IB
81483IBZ
ISL81483IP
81483IPZ
81487IB
81487IBZ
ISL81487IP
81487IPZ
TEMP. RANGE (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
PACKAGE
8 Ld SOIC*
8 Ld SOIC
8 Ld PDIP
8 Ld PDIP** (Pb-free)
8 Ld SOIC*
8 Ld SOIC* (Pb-free)
8 Ld PDIP
8 Ld PDIP** (Pb-free)
8 Ld SOIC*
8 Ld SOIC* (Pb-free)
8 Ld PDIP
8 Ld PDIP** (Pb-free)
PKG. DWG. #
M8.15
M8.15
E8.3
E8.3
M8.15
M8.15
E8.3
E8.3
M8.15
M8.15
E8.3
E8.3
*SOIC also available in Tape and Reel; Add “-T” to suffix.
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish,
which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN6050.7
July 31, 2006
ISL8487, ISL81483, ISL81487
Pin Descriptions
PIN
RO
RE
DE
DI
GND
A/Y
B/Z
V
CC
FUNCTION
Receiver output: If A > B by at least 0.2V, RO is high; If A < B by 0.2V or more, RO is low; RO = High if A and B are unconnected (floating).
Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high.
Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high. They are high impedance when DE is low.
Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low.
Ground connection.
RS-485/422 level, noninverting receiver input and noninverting driver output. Pin is an input (A) if DE = 0; pin is an output (Y) if DE = 1.
RS-485/422 level, inverting receiver input and inverting driver output. Pin is an input (B) if DE = 0; pin is an output (Z) if DE = 1.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Test Conditions: V
CC
= 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at V
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