W28J800BT90L datasheet, PDF - EEWORLD Datasheet

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W28J800BT90L: DescriptionFlash, 512KX16, 90ns, PDSO48, 12 X 20 MM, TSOP-48; Categorystorage storage; File Size464KB，49 Pages; ManufacturerWinbond Electronics Corporation; Websitehttp://www.winbond.com.tw

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W28J800BT90L Overview

Flash, 512KX16, 90ns, PDSO48, 12 X 20 MM, TSOP-48

W28J800BT90L Parametric

Parameter Name	Attribute value
Maker	Winbond Electronics Corporation
Parts packaging code	TSOP
package instruction	TSOP1, TSSOP48,.8,20
Contacts	48
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	90 ns
Other features	BOTTOM BOOT BLOCK
Spare memory width	8
startup block	BOTTOM
command user interface	YES
Data polling	NO
JESD-30 code	R-PDSO-G48
JESD-609 code	e3
length	18.4 mm
memory density	8388608 bit
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of departments/size	8,15
Number of terminals	48
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512KX16
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP1
Encapsulate equivalent code	TSSOP48,.8,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
power supply	3/3.3 V
Programming voltage	2.7 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	1.2 mm
Department size	8K,64K
Maximum standby current	0.000005 A
Maximum slew rate	0.03 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
switch bit	NO
type	NOR TYPE
width	12 mm

W28J800BT90L Preview

W28J800B/T

8M(512K

16/1M

BOOT BLOCK FLASH MEMORY

Table of Contents-

1. GENERAL DESCRIPTION.................................................................................................................. 3

2. FEATURES ......................................................................................................................................... 3

3. PRODUCT OVERVIEW ...................................................................................................................... 4

4. BLOCK DIAGRAM .............................................................................................................................. 5

Block Organization ........................................................................................................................... 6

5. PIN CONFIGURATION ....................................................................................................................... 6

6. PIN DESCRIPTION ............................................................................................................................. 7

7. PRINCIPLES OF OPERATION........................................................................................................... 8

Data Protection ................................................................................................................................ 8

8. BUS OPERATION ............................................................................................................................. 10

Read............................................................................................................................................... 10

Output Disable ............................................................................................................................... 10

Standby .......................................................................................................................................... 10

Reset .............................................................................................................................................. 10

Read Identifier Codes .................................................................................................................... 11

OTP (One Time Program) Block.................................................................................................... 12

Write ............................................................................................................................................... 12

9. COMMAND DEFINITIONS................................................................................................................ 13

Read Array Command ................................................................................................................... 15

Read Identifier Codes Command................................................................................................... 15

Read Status Register Command ................................................................................................... 15

Clear Status Register Command ................................................................................................... 16

Block Erase Command .................................................................................................................. 16

Full Chip Erase Command ............................................................................................................. 16

Word/Byte Write Command ........................................................................................................... 17

Block Erase Suspend Command ................................................................................................... 17

Word/Byte Write Suspend Command ............................................................................................ 18

Set Block and Permanent Lock-bit Commands ............................................................................. 18

Clear Block Lock-bits Command.................................................................................................... 19

OTP Program Command ............................................................................................................... 20

Block Locking by the #WP ............................................................................................................. 20

-1-

Publication Release Date: April 11, 2003

Revision A4

W28J800B/T

10. DESIGN CONSIDERATIONS ......................................................................................................... 31

Three-line Output Control............................................................................................................... 31

RY/#BY and WSM Polling.............................................................................................................. 31

Power Supply Decoupling .............................................................................................................. 31

Trace on Printed Circuit Boards.............................................................................................. 31

, V

, #RESET Transitions...................................................................................................... 31

Power-up/Down Protection ............................................................................................................ 32

Power Dissipation .......................................................................................................................... 32

Data Protection Method ................................................................................................................. 32

11. ELECTRICAL SPECIFICATIONS ................................................................................................... 33

Absolute Maximum Ratings* .......................................................................................................... 33

Operating Conditions ..................................................................................................................... 33

Capacitance(1)............................................................................................................................... 34

AC Input/Output Test Conditions ................................................................................................... 34

DC Characteristics ......................................................................................................................... 35

AC Characteristics - Read-only Operations(1) .............................................................................. 37

AC Characteristics - Write Operations(1) ...................................................................................... 40

Reset Operations ........................................................................................................................... 44

Block Erase, Full Chip Erase, Word/Byte Write And Lock-Bit Configuration Performance(3) ...... 45

12. ADDITIONAL INFORMATION......................................................................................................... 46

Recommended Operating Conditions............................................................................................ 46

13. ORDERING INFORMATION........................................................................................................... 48

14. PACKAGE DIMENSION.................................................................................................................. 48

15. VERSION HISTORY ....................................................................................................................... 49

-2-

W28J800B/T

1. GENERAL DESCRIPTION

The W28J800B/T Flash memory chip is a high-density, cost-effective, nonvolatile, read/write storage

device suited for a wide range of applications. It operates off of V

= 2.7V to 3.6V, with V

of 2.7V

to 3.6V or 11.7V to 12.3V. This low voltage operation capability enbales use in low power applications.

The IC features a boot, parameter and main-blocked architecture, as well as low voltage and

extended cycling. These features provide a highly flexible device suitable for portable terminals and

personal computers. Additionally, the enhanced suspend capabilities provide an ideal solution for both

code and data storage applications. For secure code storage applications, such as networking where

code is either directly executed out of flash or downloaded to DRAM, the device offers four levels of

protection. These are: absolute protection, enabled when V

≤

PPLK

; selective hardware blocking;

flexible software blocking; or write protection. These alternatives give designers comprehensive

control over their code security needs. The device is manufactured using 0.25

µm

process technology.

It comes in industry-standard packaging, a 48-lead TSOP, which makes it ideal for small real estate

applications.

2. FEATURES

•

Low Voltage Operation

−

= V

= 2.7V to 3.6V Single Voltage

OTP (One Time Program) Block

−

3963 word + 4 word Program only array

User-Configurable x 8 or x 16 Operation

High-Performance Read Access Time

−

90 nS (V

= 2.7V to 3.6V)

Operating Temperature

−

0° C to +70° C (W28J800BT/TT90C)

−

-40° C to +85° C (W28J800BT/TT90L)

Low Power Management

−

µA

= 3.0V) Typical Standby Current

−

Automatic Power Savings Mode Decreases

CCR

in Static Mode

−

120

µA

= 3.0V, T

=+25° C, f = 32 KHz)

Typical Read Current

•

Enhanced Automated Suspend Options

−

Word/Byte Write Suspend to Read

−

Block Erase Suspend to Word/Byte Write

−

Block Erase Suspend to Read

•

Enhanced Data Protection Features

−

Absolute Protection with V

≤

PPLK

−

Block Erase, Full Chip Erase, Word/Byte

Write and Lock-Bit Configuration Lockout

during Power Transitions

−

Block Locking with Command and #WP

−

Permanent Locking

Automated Block Erase, Full Chip Erase, Low

Power Management Word/Byte Write and

Lock-Bit Configuration

−

Command User Interface (CUI)

−

Status Register (SR)

•

SRAM-Compatible Write Interface

•

Industry-Standard Packaging

−

48-Lead TSOP

•

Nonvolatile Flash Technology

•

CMOS Process (P-type silicon substrate)

•

Not designed or rated as radiation hardened

Optimized Array Blocking Architecture

−

Two 4k-word (8k-byte) Boot Blocks

−

Six 4k-word (8k-byte) Parameter Blocks

−

Fifteen 32k-word (64k-byte) Main Blocks

−

Top or Bottom Boot Location

•

Extended Cycling Capability

−

Minimum 100,000 Block Erase Cycles

•

-3-

Publication Release Date: April 11, 2003

Revision A4

W28J800B/T

3. PRODUCT OVERVIEW

The product is a high-performance 8M-bit Boot Block Flash memory organized as 512k-word of 16

bits or 1M-byte of 8 bits. The 512k-word/1M-byte of data is arranged in two 4k-word/8k-byte boot

blocks, six 4k-word/8k-byte parameter blocks and fifteen 32k-word/64k-byte main blocks which are

individually erasable, lockable and unlockable in-system. The memory map is shown in Figure 3.

The dedicated V

pin gives complete data protection when V

≤

PPLK

A Command User Interface (CUI) serves as the interface between the system processor and internal

operation of the device. A valid command sequence written to the CUI initiates device automation. An

internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for

block erase, full chip erase, word/byte write and lock-bit configuration operations.

A block erase operation erases one of the device’s 32k-word/64k-byte blocks typically within 1.2S (3V

, 3V V

), 4k-word/8k-byte blocks typically within 0.6s (3V V

, 3V V

) independent of other

blocks. Each block can be independently erased minimum 100,000 times. Block erase suspend mode

allows system software to suspend block erase to read or write data from any other block.

Writing memory data is performed in word/byte increments of the device’s 32k-word blocks typically

within 33

µS

(3V V

, 3V V

), 64k-byte blocks typically within 31

µS

(3V V

, 3V V

), 4k-word

blocks typically within 36

µS

(3V V

, 3V V

), 8k-byte blocks typically within 32

µS

(3V V

, 3V

). Word/byte write suspend mode enables the system to read data or execute code from any other

flash memory array location.

Individual block locking uses a combination of bits, thirty-nine block lock-bits, a permanent lock-bit and

#WP pin, to lock and unlock blocks. Block lock-bits gate block erase, full chip erase and word/byte

write operations, while the permanent lock-bit gates block lock-bit modification and locked block

alternation. Lock-bit configuration operations (Set Block Lock-Bit, Set Permanent Lock-Bit and Clear

Block Lock-Bits commands) set and cleared lock-bits.

The status register indicates when the WSM’s block erase, full chip erase, word/byte write or lock-bit

configuration operation is finished.

The RY/#BY output gives an additional indicator of WSM activity by providing both a hardware signal

of status (versus software polling) and status masking (interrupt masking for background block erase,

for example). Status polling using RY/#BY minimizes both CPU overhead and system power

consumption. When low, RY/#BY indicates that the WSM is performing a block erase, full chip erase,

word/byte write or lock-bit configuration. RY/#BY-high Z indicates that the WSM is ready for a new

command, block erase is suspended (and word/byte write is inactive), word/byte write is suspended,

or the device is in reset mode.

The access time is 90 nS (t

AVQV

) over the operating temperature range and V

supply voltage range

of 2.7V to 3.6V.

The Automatic Power Savings (APS) feature substantially reduces active current when the device is in

static mode (addresses not switching). In APS mode, the typical I

CCR

current is 2

µA

(CMOS) at 3.0V

When #CE and #RESET pins are at V

, the I

CMOS standby mode is enabled. When the #RESET

pin is at V

, reset mode is enabled which minimizes power consumption and provides write

protection. A reset time (t

PHQV

) is required from #RESET switching high until outputs are valid.

Likewise, the device has a wake time (t

PHEL

) from #RESET-high until writes to the CUI are recognized.

With #RESET at V

, the WSM is reset and the status register is cleared.

-4-

W28J800B/T

Overwriting a "0" to a bit already holding a data "0" may render this bit un-erasable. In order to avoid

this potential "stuck bit" failure, when re-programming (changing data from "1" to "0") the following

should be followed:

•

Program "0" for the bit in which you want to change data from "1" to "0".

Program "1" for the bit which is already holding a data "0". (Note: Since only an erase process

can change the data from "0" to "1", programming "1" to a bit holding a data "0" will not

change the data).

For example, changing data from "10111101" to "10111100" requires "11111110" programming.

4. BLOCK DIAGRAM

DQ0 -DQ15

Output Buffer

Input Buffer

I/O Logic

Identifier

Output

Multiplexer

Status

Data

Command

User

Interface

VDD

#BYTE

#CE

#WE

#OE

#RESET

#WP

Data

Comparator

Parameter Block 0

Parameter Block 1

Parameter Block 2

Parameter Block 3

Parameter Block 4

Parameter Block 5

Boot Block 0

Main Block 13

Main Block 14

Main Block 0

Main Block 1

A1-A18

Boot Block 1

Input

Buffer

Decoder

Y-Gating

OTP Block

Write

State

Machine

RY/#BY

Program/Erase

Voltage Switch

VPP

Address

Latch

Decoder

32K-Word

(64K-Byte)

Main Blocks

x 15

VDD

VSS

Address

Counter

Figure 1. Block Diagram

-5-

Publication Release Date: April 11, 2003

Revision A4

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

W28J800BT90L Related Products

	W28J800BT90L	W28J800BT90C	W28J800TT90C
Description	Flash, 512KX16, 90ns, PDSO48, 12 X 20 MM, TSOP-48	Flash, 512KX16, 90ns, PDSO48, 12 X 20 MM, TSOP-48	Flash, 512KX16, 90ns, PDSO48, 12 X 20 MM, TSOP-48
Maker	Winbond Electronics Corporation	Winbond Electronics Corporation	Winbond Electronics Corporation
Parts packaging code	TSOP	TSOP	TSOP
package instruction	TSOP1, TSSOP48,.8,20	TSOP1, TSSOP48,.8,20	TSOP1, TSSOP48,.8,20
Contacts	48	48	48
Reach Compliance Code	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99
Maximum access time	90 ns	90 ns	90 ns
Other features	BOTTOM BOOT BLOCK	BOTTOM BOOT BLOCK	TOP BOOT BLOCK
Spare memory width	8	8	8
startup block	BOTTOM	BOTTOM	TOP
command user interface	YES	YES	YES
Data polling	NO	NO	NO
JESD-30 code	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48
JESD-609 code	e3	e3	e3
length	18.4 mm	18.4 mm	18.4 mm
memory density	8388608 bit	8388608 bit	8388608 bit
Memory IC Type	FLASH	FLASH	FLASH
memory width	16	16	16
Number of functions	1	1	1
Number of departments/size	8,15	8,15	8,15
Number of terminals	48	48	48
word count	524288 words	524288 words	524288 words
character code	512000	512000	512000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	85 °C	70 °C	70 °C
organize	512KX16	512KX16	512KX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP1	TSOP1	TSOP1
Encapsulate equivalent code	TSSOP48,.8,20	TSSOP48,.8,20	TSSOP48,.8,20
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL
power supply	3/3.3 V	3/3.3 V	3/3.3 V
Programming voltage	2.7 V	2.7 V	2.7 V
Certification status	Not Qualified	Not Qualified	Not Qualified
ready/busy	YES	YES	YES
Maximum seat height	1.2 mm	1.2 mm	1.2 mm
Department size	8K,64K	8K,64K	8K,64K
Maximum standby current	0.000005 A	0.000005 A	0.000005 A
Maximum slew rate	0.03 mA	0.03 mA	0.03 mA
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V
Nominal supply voltage (Vsup)	3 V	3 V	3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	COMMERCIAL	COMMERCIAL
Terminal surface	MATTE TIN	MATTE TIN	MATTE TIN
Terminal form	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm	0.5 mm
Terminal location	DUAL	DUAL	DUAL
switch bit	NO	NO	NO
type	NOR TYPE	NOR TYPE	NOR TYPE
width	12 mm	12 mm	12 mm

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