4 MEG x 4
FPM DRAM
DRAM
FEATURES
• Industry-standard x4 pinout, timing, functions,
and packages
• High-performance, low-power CMOS silicon-gate
process
• Single power supply (+3.3V ±0.3V or +5V ±0.5V)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, HIDDEN and CAS#-
BEFORE-RAS# (CBR)
• Optional self refresh (S) for low-power data
retention
• 11 row, 11 column addresses (2K refresh) or
12 row, 10 column addresses (4K refresh)
• FAST-PAGE-MODE (FPM) access
• 5V tolerant inputs and I/Os on 3.3V devices
MT4LC4M4B1, MT4C4M4B1
MT4LC4M4A1, MT4C4M4A1
For the latest data sheet, please refer to the Micron Web
site:
www.micronsemi.com/mti/msp/html/datasheet.html
PIN ASSIGNMENT (Top View)
24/26-Pin SOJ
V
CC
DQ0
DQ1
WE#
RAS#
**NC/A11
A10
A0
A1
A2
A3
V
CC
24/26-Pin TSOP
V
CC
V
SS
DQ0
DQ3
DQ1
DQ2
WE#
CAS#
RAS#
OE#
**NC/A11
A9
A10
A0
A8
A1
A7
A2
A6
A3
A5
V
CC
A4
V
SS
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
V
SS
DQ3
DQ2
CAS#
OE#
A9
A8
A7
A6
A5
A4
V
SS
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
OPTIONS
• Voltage
3.3V
5V
• Refresh Addressing
2,048 (2K) rows
4,096 (4K) rows
• Packages
Plastic SOJ (300 mil)
Plastic TSOP (300 mil)
• Timing
50ns access
60ns access
• Refresh Rates
Standard Refresh
Self Refresh (128ms period)
MARKING
LC
C
B1
A1
DJ
TG
-5
-6
None
S*
**NC on 2K refresh and A11 on 4K refresh options.
4 MEG x 4 FPM DRAM PART NUMBERS
PART NUMBER
MT4LC4M4B1DJ-6
MT4LC4M4B1DJ-6 S
MT4LC4M4B1TG-6
MT4LC4M4B1TG-6 S
MT4LC4M4A1DJ-6
MT4LC4M4A1DJ-6 S
MT4LC4M4A1TG-6
MT4C4M4A1TG-6 S
MT4C4M4B1DJ-6
MT4C4M4B1DJ-6 S
MT4C4M4B1TG-6
MT4C4M4B1TG-6 S
MT4C4M4A1DJ-6
MT4C4M4A1DJ-6 S
MT4C4M4A1TG-6
MT4C4M4A1TG-6 S
V
CC
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
5V
5V
5V
5V
5V
5V
5V
5V
REFRESH
ADDRESSING PACKAGE REFRESH
2K
2K
2K
2K
4K
4K
4K
4K
2K
2K
2K
2K
4K
4K
4K
4K
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
NOTE:
1. The 4 Meg x 4 FPM DRAM base number differenti-
ates the offerings in one place—MT4LC4M4B1. The
fifth field distinguishes various options: B1
designates a 2K refresh and A1 designates a 4K
refresh for FPM DRAMs.
2. The # symbol indicates signal is active LOW.
*Contact factory for availability
Part Number Example:
MT4LC4M4B1DJ
KEY TIMING PARAMETERS
SPEED
-5
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
RP
84ns
110ns
50ns
60ns
20ns
35ns
25ns
30ns
13ns
15ns
30ns
40ns
4 Meg x 4 FPM DRAM
D49_5V.p65 – Rev. 5/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
GENERAL DESCRIPTION
The 4 Meg x 4 DRAM is a randomly accessed, solid-
state memory containing 16,777,216 bits organized in
a x4 configuration. RAS# is used to latch the row
address (first 11 bits for 2K and first 12 bits for 4K). Once
the page has been opened by RAS#, CAS# is used to latch
the column address (the latter 11 bits for 2K and the
latter 10 bits for 4K; address pins A10 and A11 are “Don’t
Care”).
READ and WRITE cycles are selected with the WE#
input. A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. If WE# goes
LOW prior to CAS# going LOW, the output pins
remain open (High- Z) until the next CAS# cycle,
regardless of OE#.
A logic HIGH on WE# dictates read mode, while a
logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. An EARLY
WRITE occurs when WE# is taken LOW prior to CAS#
falling. A LATE WRITE or READ-MODIFY-WRITE
occurs when WE# falls after CAS# is taken LOW. During
EARLY WRITE cycles, the data outputs (Q) will remain
High-Z regardless of the state of OE#. During LATE
WRITE or READ-MODIFY-WRITE cycles, OE# must be
taken HIGH to disable the data outputs prior to
applying input data. If a LATE WRITE or READ-
MODIFY-WRITE is attempted while keeping OE# LOW,
no WRITE will occur, and the data outputs will drive
read data from the accessed location.
The four data inputs and the four data outputs are
routed through four pins using common I/O, and pin
direction is controlled by WE# and OE#.
The MT4LC4M4B1 and MT4LC4M4A1 must be
refreshed periodically in order to retain stored data.
Additional columns may be accessed by providing valid
column addresses, strobing CAS# and holding RAS#
LOW, thus executing faster memory cycles. Returning
RAS# HIGH terminates the page mode of operation,
i.e., closes the page.
DRAM REFRESH
Preserve correct memory cell data by maintaining
power and executing any RAS# cycle (READ, WRITE)
or RAS# REFRESH cycle (RAS#-ONLY, CBR, or HID-
DEN) so that all combinations of RAS# addresses (2,048
for 2K and 4,096 for 4K) are executed within
t
REF
(MAX), regardless of sequence. The CBR and SELF
REFRESH cycles will invoke the internal refresh counter
for automatic RAS# addressing.
An optional self refresh mode is also available the
“S” version. The self refresh feature is initiated by
performing a CBR REFRESH cycle and holding RAS#
LOW for the specified
t
RASS. The “S” option allows the
user the choice of a fully static, low-power data reten-
tion mode or a dynamic refresh mode at the extended
refresh period of 128ms, or 31.25µs per row for a 4K
refresh and 62.5µs per row for a 2K refresh, when using
a distributed CBR REFRESH. This refresh rate can be
applied during normal operation, as well as during a
standby or battery backup mode.
The self refresh mode is terminated by driving RAS#
HIGH for a minimum time of
t
RPS. This delay allows for
the completion of any internal refresh cycles that may
be in process at the time of the RAS# LOW-to-HIGH
transition. If the DRAM controller uses a distributed
CBR refresh sequence, a burst refresh is not required
upon exiting self refresh. However, if the DRAM con-
troller utilizes RAS#-ONLY or burst CBR refresh se-
quence, all rows must be refreshed with a refresh rate of
t
RC minimum prior to resuming normal operation.
FAST PAGE MODE ACCESS
Page operations allow faster data operations (READ,
WRITE or READ-MODIFY-WRITE) within a row-
address-defined page boundary. The page cycle is al-
ways initiated with a row address strobed in by RAS#,
followed by a column address strobed in by CAS#.
STANDBY
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. The chip is preconditioned for the next
cycle during the RAS# HIGH time.
4 Meg x 4 FPM DRAM
D49_5V.p65 – Rev. 5/00
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
CC
Pin Relative to V
SS
3.3V............................................. ......... -1V to +4.6V
5V................................................ ............ -1V
TO
+7V
Voltage on NC, Inputs or I/O Pins Relative to V
SS
3.3V............................................. ......... -1V to +5.5V
5V................................................ ............ -1V
TO
+7V
Operating Temperature, T
A
(ambient) .... 0°C to +70°C
Storage Temperature (plastic) ............ -55°C to +150°C
Power Dissipation ................................................... 1W
*Stresses greater than those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional opera-
tion of the device at these or any other conditions above
those indicated in the operational sections of this speci-
fication is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 5, 6) (V
CC
(MIN)
£
V
CC
£
V
CC
(MAX))
PARAMETER/CONDITION
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE:
Valid Logic 1; All inputs, I/Os and any NC
INPUT LOW VOLTAGE:
Valid Logic 0; All inputs, I/Os and any NC
INPUT LEAKAGE CURRENT:
Any input at V
IN
[0V
£
V
IN
£
V
CC
(MAX)];
All other pins not under test = 0V
OUTPUT HIGH VOLTAGE:
I
OUT
= -2mA
OUTPUT LOW VOLTAGE:
I
OUT
= 2mA
OUTPUT LEAKAGE CURRENT:
Any output at V
OUT
[0V
£
V
OUT
£
V
CC
(MAX)];
DQ is disabled and in High-Z state
SYMBOL
V
CC
V
IH
V
IL
I
I
3.3V
MIN MAX
3
2
-1.0
-2
3.6
5.5
0.8
2
5V
MIN MAX UNITS NOTES
4.5
2.4
-0.5
-2
5.5
Vcc+1
0.8
2
V
V
V
µA
24
24
V
OH
V
OL
I
OZ
2.4
–
-5
–
0.4
5
2.4
–
-5
–
0.4
5
V
V
µA
4 Meg x 4 FPM DRAM
D49_5V.p65 – Rev. 5/00
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
I
CC
OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 2, 3, 5, 6) [Vcc (MIN)
£
Vcc
£
Vcc (MAX)]
3.3V
PARAMETER/CONDITION
STANDBY CURRENT: TTL
(RAS# = CAS# = V
IH
)
STANDBY CURRENT: CMOS (non-“S” version only)
(RAS# = CAS# = other inputs = V
CC
- 0.2V)
STANDBY CURRENT: CMOS (“S” version only)
(RAS# = CAS# = other inputs = V
CC
- 0.2V)
OPERATING CURRENT: Random READ/WRITE
Average power supply current
(RAS#, CAS#, address cycling:
t
RC =
t
RC [MIN])
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS# = V
IL
, CAS#, address cycling:
t
PC =
t
PC [MIN])
REFRESH CURRENT: RAS#-ONLY
Average power supply current
(RAS# cycling, CAS# = V
IH
:
t
RC =
t
RC [MIN])
REFRESH CURRENT: CBR
Average power supply current
(RAS#, CAS#, address cycling:
t
RC =
t
RC [MIN])
REFRESH CURRENT: Extended (“S” version only)
Average power supply current: CAS# = 0.2V or
CBR cycling; RAS# =
t
RAS (MIN); WE# = V
CC
- 0.2V;
A0-A11, OE# and D
IN
= V
CC
- 0.2V or 0.2V
(D
IN
may be left open)
REFRESH CURRENT: Self (“S” version only)
Average power supply current: CBR with
RAS#
t
RASS (MIN) and CAS# held LOW;
WE# = V
CC
- 0.2V; A0-A11, OE# and
D
IN
= V
CC
- 0.2V or 0.2V (D
IN
may be left open)
5V
2K
4K
2K
4K
SYM SPEED REFRESH REFRESH REFRESH REFRESH UNITS NOTES
I
CC
1
I
CC
2
I
CC
2
ALL
ALL
ALL
-5
-6
-5
-6
-5
-6
-5
-6
ALL
I
CC
7
t
RC
1
500
150
110
100
110
100
110
100
110
100
300
1
500
150
90
80
100
90
90
80
90
80
300
1
500
150
140
130
110
100
140
130
140
130
300
1
500
150
120
110
100
90
120
110
120
110
300
mA
mA
µA
I
CC
3
mA
23
I
CC
4
mA
23
I
CC
5
mA
I
CC
6
mA
µA
4, 7
4, 7
62.5
31.25
62.5
31.25
µs
23
I
CC
8
ALL
300
300
300
300
µA
4, 7
CAPACITANCE
(Note: 6)
PARAMETER
Input Capacitance: Address pins
Input Capacitance: RAS#, CAS#, WE#, OE#
Input/Output Capacitance: DQ
SYMBOL
C
I
1
C
I
2
C
IO
MAX
5
7
7
UNITS
pF
pF
pF
4 Meg x 4 FPM DRAM
D49_5V.p65 – Rev. 5/00
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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