M58LR256GL85ZC5E datasheet, PDF

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M58LR256GL85ZC5E: Description16MX16 FLASH 1.8V PROM, 90ns, PBGA44, 8 X 10 MM, 0.50 MM PITCH, VFBGA-44; Categorystorage storage; File Size887KB，115 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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M58LR256GL85ZC5E Overview

16MX16 FLASH 1.8V PROM, 90ns, PBGA44, 8 X 10 MM, 0.50 MM PITCH, VFBGA-44

M58LR256GL85ZC5E Parametric

Parameter Name	Attribute value
Maker	STMicroelectronics
Parts packaging code	BGA
package instruction	8 X 10 MM, 0.50 MM PITCH, VFBGA-44
Contacts	44
Reach Compliance Code	unknown
ECCN code	3A991.B.1.A
Maximum access time	90 ns
startup block	BOTTOM
JESD-30 code	R-PBGA-B44
length	10 mm
memory density	268435456 bit
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of terminals	44
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-25 °C
organize	16MX16
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Programming voltage	1.8 V
Certification status	Not Qualified
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	2 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL EXTENDED
Terminal form	BALL
Terminal pitch	0.5 mm
Terminal location	BOTTOM
type	NOR TYPE
width	8 mm

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M58LR256GU, M58LR256GL

M58LR128GU, M58LR128GL

128 and 256Mbit (x16, Mux I/O, Multiple Bank, Multi-Level, Burst)

1.8V supply Flash memories

Feature summary

■

Supply voltage

– V

= 1.7V to 2.0V for program, erase and

read

– V

DDQ

= 1.7V to 2.0V for I/O Buffers

– V

= 9V for fast program

Multiplexed address/data

Synchronous / Asynchronous Read

– Synchronous Burst Read mode: 66MHz

– Random Access:

85ns (M58LR128GU/L)

90ns (M58LR256GU/L)

Synchronous Burst Read Suspend

Programming time

– 10µs typical Word program time using

Buffer Enhanced Factory Program

command

Memory organization

– Multiple Bank Memory Array:

16 Mbit (M58LR256GU/L) or

8 Mbit (M58LR128GU/L) Banks

– Parameter Blocks (Top or Bottom location)

Dual operations

– program/erase in one Bank while read in

others

– No delay between read and write

operations

Block locking

– All blocks locked at power-up

– Any combination of blocks can be locked

with zero latency

– WP for Block Lock-Down

– Absolute Write Protection with V

= V

Security

– 64 bit unique device number

– 2112 bit user programmable OTP Cells

Common Flash Interface (CFI)

■

FBGA

■

VFBGA44 (ZC) 8 x 10mm

VFBGA44 (ZB) 7.7 x 9mm

■

100,000 program/erase cycles per block

Electronic signature

– Manufacturer Code: 20h

– Top Device Codes:

M58LR256GU: 882Ch

M58LR128GU: 882Eh

– Bottom Device Codes

M58LR256GL: 882Dh

M58LR128GL: 882Fh

ECOPACK® packages available

■

June 2006

Rev 1

1/114

www.st.com

Contents

M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL

Contents

Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

2.13

2.14

2.15

Address Inputs (ADQ0-ADQ15 and A16-Amax) . . . . . . . . . . . . . . . . . . . 15

Data Input/Output (ADQ0-ADQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DDQ

supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

SSQ

ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1

3.2

3.3

3.4

3.5

3.6

Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1

4.2

4.3

4.4

Read Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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Contents

4.5

4.6

4.7

4.8

4.9

Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Buffer Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Buffer Enhanced Factory Program command . . . . . . . . . . . . . . . . . . . . . 26

4.9.1

4.9.2

4.9.3

Setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Program and Verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.10

4.11

4.12

4.13

4.14

4.15

4.16

Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Protection Register Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Set Configuration Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Block Lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Block Unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Block Lock-Down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

Program/Erase Controller status bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . 36

Erase Suspend status bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Erase status bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Program status bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

status bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Program Suspend status bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Block Protection Status Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Bank Write/Multiple Word Program status bit (SR0) . . . . . . . . . . . . . . . . 38

Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.1

6.2

6.3

6.4

6.5

6.6

6.7

Read Select bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

X-Latency bits (CR13-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Wait Polarity bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Data Output Configuration bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Wait Configuration bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Burst Type bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Valid Clock Edge bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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Contents

M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL

6.8

6.9

Wrap Burst bit (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Burst length bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.1

7.2

7.3

Asynchronous Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Synchronous Burst Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.2.1

Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Single Synchronous Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Dual operations and Multiple Bank architecture . . . . . . . . . . . . . . . . . 50

Block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9.1

9.2

9.3

9.4

9.5

Reading a block’s Lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Lock-Down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Locking operations during Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . 53

Program and Erase times and endurance cycles . . . . . . . . . . . . . . . . . 55

Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Appendix A Block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Appendix B Common Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Appendix C Flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Appendix D Command interface state tables. . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

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M58LR256GU, M58LR256GL, M58LR128GU, M58LR128GL

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

Table 45.

Table 46.

Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

M58LR256GU/L bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

M58LR128GU/L bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Factory Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Electronic Signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Protection Register locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

X-latency settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Configuration Register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Wait at the boundary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Dual operation limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Program/Erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

DC characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

DC characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Asynchronous Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Synchronous Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Reset and Power-up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

VFBGA44 8 × 10mm - 10 × 4 ball array, 0.50mm pitch,

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

VFBGA44 7.7 × 9mm - 10 × 4 ball array, 0.50mm pitch,

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

M58LR256GU - Parameter Bank block addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

M58LR256GU - Main Bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

M58LR256GU - Block addresses in Main Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

M58LR256GL - Parameter Bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

M58LR256GL - Main Bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

M58LR256GL - Block addresses in Main Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

M58LR128GU - Parameter Bank block addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

M58LR128GU - Main Bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

M58LR128GU - Block addresses in Main Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

M58LR128GL - Parameter Bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

M58LR128GL - Main Bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

M58LR128GL - Block addresses in Main Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

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When using NiosII/e or NiosII/s, the system runs normally; but when changing to NiosII/f, the system cannot run normally. Why?: I have a question about FPGA , experts please help me, thanks in advance!I am using DE0 development board, quartrsII 8.1, NiosII8.1. The system built in SOPC includes the following components: NiosII,...; eeleader FPGA/CPLD

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The USB driver receives data but the data received by the application is all zero. What is the problem? Can an expert help me?: The USB driver receives data but the data received by the application is all zero. What is the problem? The actual situation is as follows: There is a device communicating with the host via USB. On th...; pcb27889967 Embedded System

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