Output Rise and Fall Time: .................................. 5 ns (max.)
Table 1. Modulation Width Selection
SS%
0
1
W181-01, 02, 03 Output W181-51, 52, 53 Output
–1.25%
(Down Spread)
–3.75%
(Down Spread)
±0.625
(Center Spread)
±1.875%
(Center Spread)
Overview
The W181 products are one series of devices in the Cypress
PREMIS family. The PREMIS family incorporates the latest
advances in PLL spread spectrum frequency synthesizer
techniques. By frequency modulating the output with a
low-frequency carrier, peak EMI is greatly reduced. Use of this
technology allows systems to pass increasingly difficult EMI
testing without resorting to costly shielding or redesign.
In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The
Simplified Block Diagram on page 1 shows a simple imple-
mentation.
Functional Description
The W181 uses a phase-locked loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in
Figure 1.
The
input reference signal is divided by Q and fed to the phase
detector. A signal from the VCO is divided by P and fed back
to the phase detector also. The PLL will force the frequency of
the VCO output signal to change until the divided output signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q
times the reference frequency. (Note: For the W181 the output
frequency is equal to the input frequency.) The unique feature
of the Spread Spectrum Frequency Timing Generator is that a
modulating waveform is superimposed at the input to the VCO.
This causes the VCO output to be slowly swept across a
predetermined frequency band.
Page 2 of 9
Table 2. Frequency Range Selection
W181 Option#
FS2
0
0
1
1
FS1
0
1
0
1
-01, 51
(MHz)
28
≤
F
IN
≤
38
38
≤
F
IN
≤
48
46
≤
F
IN
≤
60
58
≤
F
IN
≤
75
-02, 52
(MHz)
28
≤
F
IN
≤
38
38
≤
F
IN
≤
48
N/A
N/A
-03, 53
(MHz)
N/A
N/A
46
≤
F
IN
≤
60
58
≤
F
IN
≤
75
Document #: 38-07152 Rev. *D
W181
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum
process has little impact on system performance.
Frequency Selection With SSFTG
In Spread Spectrum Frequency Timing Generation, EMI
reduction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percentage may be varied.
V
DD
Clock Input
Reference Input
Freq.
Divider
Q
Phase
Detector
Charge
Pump
Using frequency select bits (FS1:2 pins), the frequency range
can be set. Spreading percentage is set to be 1.25% or 3.75%
(see
Table 1).
A larger spreading percentage improves EMI reduction.
However, large spread percentages may either exceed
system maximum frequency ratings or lower the average
frequency to a point where performance is affected. For these
reasons, spreading percentages between 0.5% and 2.5% are
most common.
Σ
Modulating
Waveform
VCO
Post
Dividers
CLKOUT
(EMI suppressed)
Feedback
Divider
P
PLL
GND
Figure 1. Functional Block Diagram
Spread Spectrum Frequency Timing
Generation
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the ampli-
tudes of the radiated electromagnetic emissions are reduced.
This effect is depicted in
Figure 2.
As shown in
Figure 2,
a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log
10
(P) + 9*log
10
(F)
where
P
is the percentage of deviation and
F
is the frequency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 3.
This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions.
Figure 3
details the Cypress spreading pattern. Cypress does
offer options with more spread and greater EMI reduction.
Contact your local Sales representative for details on these
devices.
Document #: 38-07152 Rev. *D
Page 3 of 9
W181
EMI Reduction
SSFTG
Typical Clock
Amplitude (dB)
Amplitude (dB)
Spread
Spectrum
Enabled
Non-
Spread
Spectrum
Frequency Span (MHz)
Center spread
Frequency Span (MHz)
Down Spread
Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX.
FREQUENCY
10%
20%
30%
40%
50%
60%
70%
80%
90%
10%
20%
30%
40%
50%
60%
70%
80%
100%
90%
MIN.
Figure 3. Typical Modulation Profile
Document #: 38-07152 Rev. *D
100%
Page 4 of 9
W181
.
Absolute Maximum Conditions
[2]
Parameter
V
DD
, V
IN
T
STG
T
A
T
B
P
D
Description
Voltage on any pin with respect to GND
Storage Temperature
Operating Temperature
Ambient Temperature under Bias
Power Dissipation
Rating
–0.5 to +7.0
–65 to +150
0 to +70
–55 to +125
0.5
Unit
V
°C
°C
°C
W
DC Electrical Characteristics
:
0°C < T
A
< 70°C, V
DD
= 3.3V ±5%
Parameter
I
DD
t
ON
V
IL
V
IH
V
OL
V
OH
I
IL
I
IH
I
OL
I
OH
C
I
C
I
R
P
Z
OUT
Description
Supply Current
Power-Up Time
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
Output Low Current
Output High Current
Input Capacitance
Input Capacitance
Input Pull-Up
Resistor
[3]
Clock Output Impedance
Note 3
Note 3
@ 0.4V, V
DD
= 3.3V
@ 2.4V, V
DD
= 3.3V
All pins except CLKIN
CLKIN pin only
First locked clock cycle after Power
Good
Test Condition
Min.
–
–
–
2.4
–
2.4
–
–
–
–
–
–
–
–
Typ.
18
–
–
–
–
–
–
–
15
15
v
6
500
25
Max.
32
5
0.8
–
0.4
–
–100
10
–
–
7
10
–
–
Unit
mA
ms
V
V
V
V
µA
µA
mA
mA
pF
pF
k
Ω
Ω
DC Electrical Characteristics:
0°C < T
A
< 70°C, V
DD
= 5V ±10%
Parameter
I
DD
t
ON
V
IL
V
IH
V
OL
V
OH
I
IL
I
IH
I
OL
I
OH
C
I
C
I
R
P
Description
Supply Current
Power-Up Time
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
Output Low Current
Output High Current
Input Capacitance
Input Capacitance
Input Pull-Up Resistor
Note 3
Note 3
@ 0.4V, V
DD
= 5V
@ 2.4V, V
DD
= 5V
All pins except CLKIN
CLKIN pin only
6
500
24
24
7
10
2.4
–100
10
0.7V
DD
0.4
First locked clock cycle after
Power Good
Test Condition
Min.
Typ.
30
Max.
50
5
0.15V
DD
Unit
mA
ms
V
V
V
V
µA
µA
mA
mA
pF
pF
kΩ
Notes:
1. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at
these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may
affect reliability
2. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up.
3. Inputs FS1:2 have a pull-up resistor; Input SSON# has a pull-down resistor.
京公网安备 11010802033920号
EEWORLD
