W18101G datasheet, PDF - EEWORLD Datasheet

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W18101G: Description75MHz, OTHER CLOCK GENERATOR, PDSO8, 0.150 INCH, MS-012, SOIC-8; CategoryThe embedded processor and controller Microcontrollers and processors; File Size184KB，9 Pages; ManufacturerCypress Semiconductor

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W18101G Overview

75MHz, OTHER CLOCK GENERATOR, PDSO8, 0.150 INCH, MS-012, SOIC-8

W18101G Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	SOIC
package instruction	SOP,
Contacts	8
Reach Compliance Code	unknown
Other features	ALSO OPERATES AT 5V SUPPLY
JESD-30 code	R-PDSO-G8
JESD-609 code	e0
length	4.889 mm
Number of terminals	8
Maximum operating temperature	70 °C
Minimum operating temperature
Maximum output clock frequency	75 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Master clock/crystal nominal frequency	75 MHz
Certification status	Not Qualified
Maximum seat height	1.727 mm
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.8985 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER

W18101G Preview

W181

Peak-Reducing EMI Solution

Features

•

Cypress PREMIS™ family offering

• Generates an EMI optimized clocking signal

at the output

• Selectable input to output frequency

• Single 1.25% or 3.75% down or center spread output

• Integrated loop filter components

• Operates with a 3.3V or 5V supply

• Low-power CMOS design

• Available in 8-pin small outline integrated circuit

(SOIC) or 14-pin thin shrink small outline package

(TSSOP select options only)

Simplified Block Diagram

3.3 or 5.0V

Pin Configurations

SOIC

W181-01/51

CLKIN or X1

NC or X2

GND

SS%

FS2

FS1

VDD

CLKOUT

XTAL

Input

40 MHz

Max.

W181

Spread Spectrum

Output

(EMI suppressed)

CLKIN or X1

NC or X2

GND

3.3 or 5.0V

SS%

SSON#

FS1

VDD

CLKOUT

TSSOP

FS2

CLKIN or X1

Oscillator or

Reference Input

FS1

VDD

CLKOUT

W181-02/03

W181-52/53

W181-01

W181

Spread Spectrum

Output

(EMI suppressed)

NC or X2

GND

SS%

Cypress Semiconductor Corporation

Document #: 38-07152 Rev. *D

•

3901 North First Street

•

San Jose

CA 95134

•

408-943-2600

Revised July 06, 2004

W181

Pin Definitions

Pin Name

CLKOUT

CLKIN or X1

Pin No.

(SOIC)

Pin No.

(TSSOP)(-01)

Type

Pin Description

Output Modulated Frequency:

Frequency modulated copy of the

unmodulated input clock (SSON# asserted).

Crystal Connection or External Reference Frequency Input:

This pin

has dual functions. It may either be connected to an external crystal, or

to an external reference clock.

Crystal Connection:

If using an external reference, this pin must be left

unconnected.

Spread Spectrum Control (Active LOW):

Asserting this signal (active

LOW) turns the internal modulation waveform on. This pin has an internal

pull-down resistor.

Frequency Selection Bit(s) 1 and 2:

These pins select the frequency

range of operation. Refer to

Table 2.

These pins have internal pull-up

resistors.

Modulation Width Selection:

When Spread Spectrum feature is turned

on, this pin is used to select the amount of variation and peak EMI

reduction that is desired on the output signal. This pin has an internal

pull-up resistor.

Power Connection:

Connected to 3.3V or 5V power supply.

Ground Connection:

Connect all ground pins to the common system

ground plane.

No Connection

NC or X2

SSON#

8(02/03/52/53)

FS1:2

7, 8 (01/51)

12, 1

SS%

VDD

GND

5, 7, 9, 11, 13,

Key Specifications

Supply Voltages: .........................................V

= 3.3V ± 5%

.................................................................or V

= 5V ± 10%

Frequency Range: ............................ 28 MHz

≤

75 MHz

Crystal Reference Range.................. 28 MHz

≤

40 MHz

Cycle to Cycle Jitter: ....................................... 300 ps (max.)

Selectable Spread Percentage: ................... 1.25% or 3.75%

Output Duty Cycle: ............................... 40/60% (worst case)

Output Rise and Fall Time: .................................. 5 ns (max.)

Table 1. Modulation Width Selection

SS%

W181-01, 02, 03 Output W181-51, 52, 53 Output

–1.25%

(Down Spread)

–3.75%

(Down Spread)

±0.625

(Center Spread)

±1.875%

(Center Spread)

Overview

The W181 products are one series of devices in the Cypress

PREMIS family. The PREMIS family incorporates the latest

advances in PLL spread spectrum frequency synthesizer

techniques. By frequency modulating the output with a

low-frequency carrier, peak EMI is greatly reduced. Use of this

technology allows systems to pass increasingly difficult EMI

testing without resorting to costly shielding or redesign.

In a system, not only is EMI reduced in the various clock lines,

but also in all signals which are synchronized to the clock.

Therefore, the benefits of using this technology increase with

the number of address and data lines in the system. The

Simplified Block Diagram on page 1 shows a simple imple-

mentation.

Functional Description

The W181 uses a phase-locked loop (PLL) to frequency

modulate an input clock. The result is an output clock whose

frequency is slowly swept over a narrow band near the input

signal. The basic circuit topology is shown in

Figure 1.

The

input reference signal is divided by Q and fed to the phase

detector. A signal from the VCO is divided by P and fed back

to the phase detector also. The PLL will force the frequency of

the VCO output signal to change until the divided output signal

and the divided reference signal match at the phase detector

input. The output frequency is then equal to the ratio of P/Q

times the reference frequency. (Note: For the W181 the output

frequency is equal to the input frequency.) The unique feature

of the Spread Spectrum Frequency Timing Generator is that a

modulating waveform is superimposed at the input to the VCO.

This causes the VCO output to be slowly swept across a

predetermined frequency band.

Page 2 of 9

Table 2. Frequency Range Selection

W181 Option#

FS2

FS1

-01, 51

(MHz)

≤

-02, 52

(MHz)

≤

N/A

-03, 53

(MHz)

N/A

≤

Document #: 38-07152 Rev. *D

W181

Because the modulating frequency is typically 1000 times

slower than the fundamental clock, the spread spectrum

process has little impact on system performance.

Frequency Selection With SSFTG

In Spread Spectrum Frequency Timing Generation, EMI

reduction depends on the shape, modulation percentage, and

frequency of the modulating waveform. While the shape and

frequency of the modulating waveform are fixed for a given

frequency, the modulation percentage may be varied.

Clock Input

Reference Input

Freq.

Divider

Phase

Detector

Charge

Pump

Using frequency select bits (FS1:2 pins), the frequency range

can be set. Spreading percentage is set to be 1.25% or 3.75%

(see

Table 1).

A larger spreading percentage improves EMI reduction.

However, large spread percentages may either exceed

system maximum frequency ratings or lower the average

frequency to a point where performance is affected. For these

reasons, spreading percentages between 0.5% and 2.5% are

most common.

Modulating

Waveform

VCO

Post

Dividers

CLKOUT

(EMI suppressed)

Feedback

Divider

PLL

GND

Figure 1. Functional Block Diagram

Spread Spectrum Frequency Timing

Generation

The device generates a clock that is frequency modulated in

order to increase the bandwidth that it occupies. By increasing

the bandwidth of the fundamental and its harmonics, the ampli-

tudes of the radiated electromagnetic emissions are reduced.

This effect is depicted in

Figure 2.

As shown in

Figure 2,

a harmonic of a modulated clock has a

much lower amplitude than that of an unmodulated signal. The

reduction in amplitude is dependent on the harmonic number

and the frequency deviation or spread. The equation for the

reduction is:

dB = 6.5 + 9*log

(P) + 9*log

(F)

where

is the percentage of deviation and

is the frequency

in MHz where the reduction is measured.

The output clock is modulated with a waveform depicted in

Figure 3.

This waveform, as discussed in “Spread Spectrum

Clock Generation for the Reduction of Radiated Emissions” by

Bush, Fessler, and Hardin produces the maximum reduction

in the amplitude of radiated electromagnetic emissions.

Figure 3

details the Cypress spreading pattern. Cypress does

offer options with more spread and greater EMI reduction.

Contact your local Sales representative for details on these

devices.

Document #: 38-07152 Rev. *D

Page 3 of 9

W181

EMI Reduction

SSFTG

Typical Clock

Amplitude (dB)

Spread

Spectrum

Enabled

Non-

Spread

Spectrum

Frequency Span (MHz)

Center spread

Frequency Span (MHz)

Down Spread

Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation

MAX.

FREQUENCY

10%

20%

30%

40%

50%

60%

70%

80%

90%

10%

20%

30%

40%

50%

60%

70%

80%

100%

90%

MIN.

Figure 3. Typical Modulation Profile

Document #: 38-07152 Rev. *D

100%

Page 4 of 9

W181

Absolute Maximum Conditions

[2]

Parameter

, V

STG

Description

Voltage on any pin with respect to GND

Storage Temperature

Operating Temperature

Ambient Temperature under Bias

Power Dissipation

Rating

–0.5 to +7.0

–65 to +150

0 to +70

–55 to +125

0.5

Unit

°C

DC Electrical Characteristics

0°C < T

< 70°C, V

= 3.3V ±5%

Parameter

OUT

Description

Supply Current

Power-Up Time

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Input Low Current

Input High Current

Output Low Current

Output High Current

Input Capacitance

Input Pull-Up

Resistor

[3]

Clock Output Impedance

Note 3

@ 0.4V, V

= 3.3V

@ 2.4V, V

= 3.3V

All pins except CLKIN

CLKIN pin only

First locked clock cycle after Power

Good

Test Condition

Min.

–

2.4

–

2.4

–

Typ.

–

500

Max.

0.8

–

0.4

–

–100

–

Unit

µA

Ω

DC Electrical Characteristics:

0°C < T

< 70°C, V

= 5V ±10%

Parameter

Description

Supply Current

Power-Up Time

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Input Low Current

Input High Current

Output Low Current

Output High Current

Input Capacitance

Input Pull-Up Resistor

Note 3

@ 0.4V, V

= 5V

@ 2.4V, V

= 5V

All pins except CLKIN

CLKIN pin only

500

2.4

–100

0.7V

0.4

First locked clock cycle after

Power Good

Test Condition

Min.

Typ.

Max.

0.15V

Unit

µA

kΩ

Notes:

1. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at

these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may

affect reliability

2. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up.

3. Inputs FS1:2 have a pull-up resistor; Input SSON# has a pull-down resistor.

Document #: 38-07152 Rev. *D

Page 5 of 9

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W18101G Related Products

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Description	75MHz, OTHER CLOCK GENERATOR, PDSO8, 0.150 INCH, MS-012, SOIC-8	Clock Generator, 75MHz, CMOS, PDSO14, 4.40 MM, TSSOP-14	Clock Generator, 75MHz, CMOS, PDSO8, 0.150 INCH, MS-012, SOIC-8	48MHz, OTHER CLOCK GENERATOR, PDSO8, 0.150 INCH, MS-012, SOIC-8	Clock Generator, 48MHz, CMOS, PDSO8, 0.150 INCH, MS-012, SOIC-8	Clock Generator, 75MHz, CMOS, PDSO8, 0.150 INCH, MS-012, SOIC-8	75MHz, OTHER CLOCK GENERATOR, PDSO8, 0.150 INCH, MS-012, SOIC-8
Maker	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor
Parts packaging code	SOIC	TSSOP	SOIC	SOIC	SOIC	SOIC	SOIC
package instruction	SOP,	TSSOP,	SOP,	0.150 INCH, MS-012, SOIC-8	SOP,	SOP,	SOP,
Contacts	8	14	8	8	8	8	8
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown
Other features	ALSO OPERATES AT 5V SUPPLY	ALSO OPERATES AT 5V SUPPLY	ALSO OPERATES AT 5V SUPPLY	ALSO OPERATES AT 5V SUPPLY	ALSO OPERATES AT 5V SUPPLY	ALSO OPERATES AT 5V SUPPLY	ALSO OPERATES AT 5V SUPPLY
JESD-30 code	R-PDSO-G8	R-PDSO-G14	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8
length	4.889 mm	5 mm	4.889 mm	4.889 mm	4.889 mm	4.889 mm	4.889 mm
Number of terminals	8	14	8	8	8	8	8
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
Maximum output clock frequency	75 MHz	75 MHz	75 MHz	48 MHz	48 MHz	75 MHz	75 MHz
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	TSSOP	SOP	SOP	SOP	SOP	SOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE
Master clock/crystal nominal frequency	75 MHz	75 MHz	75 MHz	48 MHz	48 MHz	75 MHz	75 MHz
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.727 mm	1.1 mm	1.727 mm	1.727 mm	1.727 mm	1.727 mm	1.727 mm
Maximum supply voltage	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V
Minimum supply voltage	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V
Nominal supply voltage	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	0.65 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
width	3.8985 mm	4.4 mm	3.8985 mm	3.8985 mm	3.8985 mm	3.8985 mm	3.8985 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER
ECCN code	-	EAR99	EAR99	-	EAR99	EAR99	-

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