or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
5kmx_12.2
Lattice Semiconductor
Figure 1. ispXPLD 5000MX Block Diagram
PROGRAM
ispXPLD 5000MX Family Data Sheet
TDO
V
CCJ
GND
TMS
TCK
V
CC
ISP Port
V
CCO0
V
REF0
sysIO
Bank 0
OSA
TDI
V
CCO3
V
REF3
MFB
MFB
sysIO
Bank 3
OSA
MFB
GCLCK0
V
CCP
GNDP
GCLK1
sysIO
Bank 1
Optional
sysCONFIG
Interface
MFB
GCLCK3
Global
Routing
Pool
(GRP)
sysCLOCK
PLL 0
sysCLOCK
PLL 1
GCLK2
MFB
MFB
sysIO
Bank 2
RESET
GOE0
GOE1
V
REF2
V
CCO2
OSA
OSA
V
REF1
V
CCO1
MFB
MFB
Introduction
The ispXPLD 5000MX family represents a new class of device, referred to as the eXpanded Programmable Logic
Devices (XPLDs). These devices extend the capability of Lattice’s popular SuperWIDE ispMACH 5000 architecture
by providing flexible memory capability. The family supports single- or dual-port SRAM, FIFO, and ternary CAM
operation. Extra logic has also been included to allow efficient implementation of arithmetic functions. In addition,
sysCLOCK PLLs and sysIO interfaces provide support for the system-level needs of designers.
The devices provide designers with a convenient one-chip solution that provides logic availability at boot-up, design
security, and extreme reconfigurability. The use of advanced process technology provides industry-leading perfor-
mance with combinatorial propagation delay as low as 4.0ns, 2.8ns clock-to-out delay, 2.2ns set-up time, and oper-
ating frequency up to 300MHz. This performance is coupled with low static and dynamic power consumption. The
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